Custom IC Design

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Discussion

QRC extraction problem

Category: Custom IC Design

By umais

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updated over 8 years ago by Andrew Beckett

3 replies • 15451 views
Discussion

Problem saving intrinsic parameters using save statement save NM0:all

Category: Custom IC Design

By Bean1234

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updated over 8 years ago by Andrew Beckett

1 replies • 1795 views
Discussion

Storing config of a cell in a file/cellview

Category: Custom IC Design

By itos

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updated over 8 years ago by Andrew Beckett

3 replies • 2012 views
Discussion

BER test setup in cadence

Category: Custom IC Design

By EngrZM

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started over 8 years ago

0 replies • 13814 views
Discussion

Cadence Virtuoso: Import a large verilog netlist to cadence schematic

Category: Custom IC Design

By oAwad

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updated over 8 years ago by Andrew Beckett

3 replies • 18760 views
Discussion

layout dynamic selection accessibility?

Category: Custom IC Design

By yeh1

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updated over 8 years ago by Andrew Beckett

1 replies • 13762 views
Discussion

import physical verilog netlist in Virtuoso

Category: Custom IC Design

By oAwad

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updated over 8 years ago by Andrew Beckett

5 replies • 25442 views
Discussion

Assura problems with feedthrough caps

Category: Custom IC Design

By ManuelSuarez

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updated over 8 years ago by ManuelSuarez

2 replies • 13977 views
Discussion

Cadence Liberate: Path delays all zero in exported of verilog models

Category: Custom IC Design

By marten

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updated over 8 years ago by marten

6 replies • 16475 views
Discussion

Spectre: use models on a per module basis?

Category: Custom IC Design

By dontpanic

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updated over 8 years ago by dontpanic

4 replies • 16747 views
Discussion

A few questions regarding using PSS for rectifier design

Category: Custom IC Design

By MenghanSun

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updated over 8 years ago by Andrew Beckett

5 replies • 16239 views
Discussion

Generating a bit stream in Virtuoso

Category: Custom IC Design

By oAwad

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updated over 8 years ago by Andrew Beckett

1 replies • 17081 views
Discussion

Can't open cells in hierarchical schematic in Virtuoso

Category: Custom IC Design

By oAwad

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updated over 8 years ago by Andrew Beckett

1 replies • 3817 views
Discussion

layer map file for GDS transfer to virtuoso

Category: Custom IC Design

By oAwad

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updated over 8 years ago by oAwad

9 replies • 31574 views
Discussion

Sweeping 2 variables (at a time) in Parametric analysis

Category: Custom IC Design

By EngrZM

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updated over 8 years ago by Andrew Beckett

6 replies • 27193 views

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