Custom IC Design

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[URI] Issues usign the scaleparam function in the URI (Unified Reliability Interface) with multiple aging models.

Category: Custom IC Design

By FAVG

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updated over 8 years ago by Andrew Beckett

1 replies • 14341 views
Discussion

Reg channel length in gpdk045

Category: Custom IC Design

By Pasupathy KR

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started over 8 years ago

0 replies • 13864 views
Discussion

Modifying extracted netlist for post layout simulation

Category: Custom IC Design

By Hasan91

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started over 8 years ago

0 replies • 14017 views
Discussion

Problem in QRC Extraction due to inconsistent models

Category: Custom IC Design

By Casp

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updated over 8 years ago by DeepAG

3 replies • 14250 views
Discussion

Floorplanner generate physical hierarchy

Category: Custom IC Design

By RVERP

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started over 8 years ago

0 replies • 13761 views
Discussion

[ADE XL] Compiling verilog-A module

Category: Custom IC Design

By Seokhyun Jeong

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started over 8 years ago

0 replies • 14388 views
Discussion

Layout XL: how to set default options for Selection Protection?

Category: Custom IC Design

By dontpanic

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updated over 8 years ago by dontpanic

4 replies • 16759 views
Discussion

How to subtract a wire/path from a polygon

Category: Custom IC Design

By JWHoll

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updated over 8 years ago by Andrew Beckett

1 replies • 3913 views
Discussion

QRC (EXT91) always fails

Category: Custom IC Design

By Zach

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updated over 8 years ago by Quek

6 replies • 17506 views
Discussion

How to store a value/Store function in Verilog-A/AMS

Category: Custom IC Design

By Hasan91

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updated over 8 years ago by Hasan91

2 replies • 2277 views
Discussion

IQ cross-talk: simulation artefact?

Category: Custom IC Design

By itos

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updated over 8 years ago by itos

4 replies • 16046 views
Discussion

Error while simulating verilog-A block

Category: Custom IC Design

By tangudubharat

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updated over 8 years ago by tangudubharat

6 replies • 17812 views
Discussion

Sampled point inaccuracy in AMS simulation

Category: Custom IC Design

By auran

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updated over 8 years ago by auran

4 replies • 16382 views
Discussion

VHDL-AMS library issue?

Category: Custom IC Design

By srana01

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updated over 8 years ago by Andrew Beckett

1 replies • 15464 views
Discussion

ADE-XL doesn't pick up readic initial condition file/ How to properly pass initial condition setup into ADEXL?

Category: Custom IC Design

By RFAnalog123

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updated over 8 years ago by Andrew Beckett

2 replies • 3708 views

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