Custom IC Design

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Discussion

Guidelines for the Custom IC Design Forum

Category: Custom IC Design

By Andrew Beckett

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started over 14 years ago

0 replies • 31508 views
Discussion

Problems with Virtuoso ADE Explorer

Category: Custom IC Design

By FZ20251125769

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updated 5 hours ago by Andrew Beckett

3 replies • 116 views
Discussion

significant digits in ADE assembler output expressions

Category: Custom IC Design

By an wx

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updated 11 hours ago by an wx

5 replies • 556 views
Discussion

Two-Tone Harmonic Balance Noise Settings: "Relative Harmonic" and "Reference Side-Band"

Category: Custom IC Design

By YX202508199356

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updated 23 hours ago by YX202508199356

5 replies • 813 views
Discussion

Standard Deviation Summary in Monte Carlo Simulations Across Multiple Corners

Category: Custom IC Design

By alho1

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updated 1 day ago by alho1

3 replies • 211 views
Discussion

How to set add. Spectre MC options in Assember GUI?

Category: Custom IC Design

By StephanWeber

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updated 4 days ago by Andrew Beckett

3 replies • 322 views
Discussion

Transient noise contribution works in spectre but failed in APS.

Category: Custom IC Design

By zuiying

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started 5 days ago

0 replies • 178 views
Discussion

Specifying variable as a parametric sweep in ADE Explorer (when the parametric weep involves another variable)

Category: Custom IC Design

By msharma

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updated 7 days ago by Andrew Beckett

1 replies • 289 views
Discussion

Getting more data after MC run directly in the Results table?

Category: Custom IC Design

By StephanWeber

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updated 7 days ago by Andrew Beckett

18 replies • 1401 views
Discussion

Wildcard '*' does not match any net in spectre save statement

Category: Custom IC Design

By msharma

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updated 7 days ago by msharma

4 replies • 409 views
Discussion

$fscanf and $fget do not work when any portion of Verilog-A file is encrypted

Category: Custom IC Design

By ConradJ

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updated 7 days ago by ConradJ

2 replies • 328 views
Discussion

ahdlvar not saved although saveahdlvars=all is set

Category: Custom IC Design

By StephanWeber

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updated 8 days ago by StephanWeber

2 replies • 278 views
Discussion

Failing to extract parasitics from layout - capgen file is missing

Category: Custom IC Design

By EG202602196052

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started 12 days ago

0 replies • 215 views
Discussion

Very Basic Wire naming question

Category: Custom IC Design

By HL20260227511

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updated 12 days ago by Andrew Beckett

1 replies • 338 views
Discussion

get the difference between two wave forms after parametric sweep.

Category: Custom IC Design

By Svilen64

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updated 14 days ago by Svilen64

5 replies • 544 views

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