Custom IC Design

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Discussion

noise sim always report 0% of Total

Category: Custom IC Design

By monglebest

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updated over 4 years ago by Andrew Beckett

8 replies • 14691 views
Discussion

Working model for MDL language - A query

Category: Custom IC Design

By MicheleAncis

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updated over 4 years ago by FormerMember

2 replies • 2063 views
Discussion

Adding wreal input and output bus in verilog-AMS

Category: Custom IC Design

By RFStuff

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updated over 4 years ago by RFStuff

5 replies • 16489 views
Discussion

HISIM-HV models

Category: Custom IC Design

By pejmank

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updated over 4 years ago by Andrew Beckett

2 replies • 12380 views
Discussion

Verilog-A white_noise function returns 0 in transient noise simulation

Category: Custom IC Design

By threepwood06

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updated over 4 years ago by threepwood06

4 replies • 13253 views
Discussion

Canceling out the parasitic diode in Layout

Category: Custom IC Design

By Hossein Eslahi

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started over 4 years ago

0 replies • 11940 views
Discussion

Current density check for layout design

Category: Custom IC Design

By Senan

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updated over 4 years ago by Senan

4 replies • 14566 views
Discussion

"ERROR: attempt to access a quantity that depends on the time derivative" in Verilog-A

Category: Custom IC Design

By rhanna

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updated over 4 years ago by Andrew Beckett

13 replies • 6266 views
Discussion

Bindkeys in ADE Explorer/Assembler

Category: Custom IC Design

By crossi

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updated over 4 years ago by crossi

5 replies • 3010 views
Discussion

illegal connection CAD warning message

Category: Custom IC Design

By Senan

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started over 4 years ago

0 replies • 11725 views
Discussion

"ncelab: *E,CUVPOM " Errors... is invalid or has multiple connections

Category: Custom IC Design

By RFStuff

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updated over 4 years ago by Andrew Beckett

1 replies • 9323 views
Discussion

Issues in using a Verilog-A output as input to a Verilog-AMS block

Category: Custom IC Design

By RFStuff

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updated over 4 years ago by Andrew Beckett

2 replies • 13924 views
Discussion

LVS fails "nothing in layout"

Category: Custom IC Design

By nicola91it

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updated over 4 years ago by Reyvandi

4 replies • 8766 views
Discussion

issue in launching Technology file manager

Category: Custom IC Design

By skillEater

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updated over 4 years ago by Andrew Beckett

4 replies • 12172 views
Discussion

Define 2D parameter array in Verilog-A

Category: Custom IC Design

By rhanna

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updated over 4 years ago by Andrew Beckett

3 replies • 15338 views

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