Custom IC Design

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Understanding 'stop' layers for Layout XL connectivity extraction

Category: Custom IC Design

By Lynks

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updated over 11 years ago by Andrew Beckett

2 replies • 7214 views
Discussion

Global Nets

Category: Custom IC Design

By MAAASD

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updated over 11 years ago by MAAASD

2 replies • 14979 views
Discussion

Custom coil design

Category: Custom IC Design

By apaj

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updated over 11 years ago by Quek

1 replies • 14916 views
Discussion

assura LVS unbound devices are IO cells

Category: Custom IC Design

By zczc99

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updated over 11 years ago by Quek

1 replies • 15245 views
Discussion

cdb2oa error help!

Category: Custom IC Design

By blessingbox

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updated over 11 years ago by Quek

1 replies • 14076 views
Discussion

Scale factor or unit problem in virtuoso schematic editor

Category: Custom IC Design

By simbamford

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updated over 11 years ago by Quek

1 replies • 14908 views
Discussion

Virtuoso XL editing capability is not enabled

Category: Custom IC Design

By ag2888

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updated over 11 years ago by Quek

1 replies • 14741 views
Discussion

Measuring device parameters with Assura

Category: Custom IC Design

By PietroUser

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updated over 11 years ago by Quek

1 replies • 13617 views
Discussion

Calculating the intersection point of 2 waveforms using the calculator

Category: Custom IC Design

By ag2888

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updated over 11 years ago by ag2888

2 replies • 19357 views
Discussion

auCdl view and loading CDF port order through CIW?

Category: Custom IC Design

By yayla

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updated over 11 years ago by yayla

1 replies • 16116 views
Discussion

Stop Time in Transient Analysis

Category: Custom IC Design

By Hadi Hayati

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updated over 11 years ago by Tawna

6 replies • 21953 views
Discussion

Can gzipped netlist be used in spectre?

Category: Custom IC Design

By sram8t

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updated over 11 years ago by Tawna

1 replies • 13820 views
Discussion

Unable to get license feature

Category: Custom IC Design

By moo911940

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updated over 11 years ago by skillUser

1 replies • 14399 views
Discussion

Best way to make a serial stream (SPI) for VPWLF?

Category: Custom IC Design

By bpdegnan

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updated over 11 years ago by Andrew Beckett

2 replies • 14501 views
Discussion

ADEGXL global optimisation runs only 9 jobs in parallel

Category: Custom IC Design

By vamshiky

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updated over 11 years ago by vamshiky

2 replies • 13974 views

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