Custom IC Design

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[Virtuoso] Weird issue with netlist generation

Category: Custom IC Design

By stanzani

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updated over 8 years ago by alin mocanu

5 replies • 16760 views
Discussion

Modifying a string passed through pPar()

Category: Custom IC Design

By Roderick

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updated over 8 years ago by Andrew Beckett

1 replies • 15385 views
Discussion

Run Virtuoso 64bit

Category: Custom IC Design

By Paludo

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updated over 8 years ago by FormerMember

10 replies • 22358 views
Discussion

Warning message about OS compatibility while invoking virtuoso

Category: Custom IC Design

By tangudubharat

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updated over 8 years ago by Andrew Beckett

7 replies • 28361 views
Discussion

Basics of PDK

Category: Custom IC Design

By PyQtPRO

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updated over 8 years ago by PyQtPRO

4 replies • 33310 views
Discussion

Spectrum assistant for FFT - How is the signal freq decided?

Category: Custom IC Design

By jdp721

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updated over 8 years ago by Andrew Beckett

5 replies • 5007 views
Discussion

power drop not seen in av_extracted simulation

Category: Custom IC Design

By primemath

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updated over 8 years ago by Andrew Beckett

1 replies • 13421 views
Discussion

probe different point on power nets in av_extracted view

Category: Custom IC Design

By primemath

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updated over 8 years ago by primemath

2 replies • 14672 views
Discussion

"Report Parasitics" cannot be Clicked

Category: Custom IC Design

By canbaltaci

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updated over 8 years ago by canbaltaci

2 replies • 2084 views
Discussion

Generating a random signal in Virtuoso

Category: Custom IC Design

By Donatello

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updated over 8 years ago by vaity

2 replies • 17061 views
Discussion

LVS error while connecting bulk with source

Category: Custom IC Design

By saikatc

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started over 8 years ago

0 replies • 16065 views
Discussion

BSIM4 Model parameters significance

Category: Custom IC Design

By JagdishP

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updated over 8 years ago by Andrew Beckett

1 replies • 17672 views
Discussion

Insert a tangent line into a plot

Category: Custom IC Design

By CESA

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updated over 8 years ago by Andrew Beckett

13 replies • 23772 views
Discussion

Verilog Netlister compatible net-separator in OA ?

Category: Custom IC Design

By Emulator

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updated over 8 years ago by Emulator

10 replies • 17702 views
Discussion

Highlighting a group of nets which match a particular regular expression

Category: Custom IC Design

By debaabed

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updated over 8 years ago by debaabed

2 replies • 13929 views

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