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Custom IC Design

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  • Discussion

    VerilogA module instance parameter override weird behavior

    Category: Custom IC Design

    By AAbdelRahman

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    updated over 4 years ago by AAbdelRahman

    7 replies • 14704 views
  • Discussion

    Thermal noise modeling

    Category: Custom IC Design

    By mahdiee86

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    updated over 4 years ago by Andrew Beckett

    5 replies • 13829 views
  • Discussion

    Assembler-4040 Failed to fetch results from Matlab script

    Category: Custom IC Design

    By Brad RFeng

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    updated over 4 years ago by Andrew Beckett

    1 replies • 9949 views
  • Discussion

    Maestro file become very large

    Category: Custom IC Design

    By delgsy

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    updated over 4 years ago by delgsy

    2 replies • 10770 views
  • Discussion

    Multipart Path Dependent Separation and Multiple Master Paths

    Category: Custom IC Design

    By Kevin Buck

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    updated over 4 years ago by Kevin Buck

    4 replies • 11828 views
  • Discussion

    5 Terminal MOSFET to exploit the Bipolar Operation of MOSFET

    Category: Custom IC Design

    By Zahid1234

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    updated over 4 years ago by Andrew Beckett

    1 replies • 11076 views
  • Discussion

    Verilog-A Parser shows an error but simulation runs successfully with 0 errors

    Category: Custom IC Design

    By ElZorro

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    updated over 4 years ago by ElZorro

    2 replies • 13449 views
  • Discussion

    Conditional netlisting of instance depending on CDF parameter value

    Category: Custom IC Design

    By JackCadnece

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    updated over 4 years ago by JackCadnece

    2 replies • 10746 views
  • Discussion

    Liberate - Constraint search failed

    Category: Custom IC Design

    By iamKarthikBK

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    updated over 4 years ago by iamKarthikBK

    4 replies • 2774 views
  • Discussion

    How to query the Assembler results database for an evaluated expression?

    Category: Custom IC Design

    By Brad RFeng

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    updated over 4 years ago by Andrew Beckett

    5 replies • 12299 views
  • Discussion

    user defined parameter in dynamic parameter transient simulation

    Category: Custom IC Design

    By GirishW

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    updated over 4 years ago by GirishW

    2 replies • 13769 views
  • Discussion

    Moving average offset in verilogA

    Category: Custom IC Design

    By jorgevdelacruzN

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    updated over 4 years ago by slim15

    2 replies • 14700 views
  • Discussion

    Layout Instantiation shows a line

    Category: Custom IC Design

    By amssshubham

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    updated over 4 years ago by Andrew Beckett

    1 replies • 9678 views
  • Discussion

    print montecarlo correlation table

    Category: Custom IC Design

    By Michael Figueiredo

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    updated over 4 years ago by Andrew Beckett

    1 replies • 10376 views
  • Discussion

    How to point to a CDL netlist in my config view

    Category: Custom IC Design

    By Svilen64

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    updated over 4 years ago by Andrew Beckett

    1 replies • 11207 views
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