Custom IC Design

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Discussion

Some parameters not appearing in "vsin" source from AnalogLib

Category: Custom IC Design

By jdp721
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updated over 9 years ago by jdp721

2 replies • 2854 views
Discussion

Is NeoCell a standalone product? Can it exist without Virtuoso?

Category: Custom IC Design

By Anonymous
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updated over 9 years ago by Andrew Beckett

1 replies • 13422 views
Discussion

Loading corner sim results for sims run using Ocean script for Cadence IC 6.1.6

Category: Custom IC Design

By ag2888
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updated over 9 years ago by Andrew Beckett

3 replies • 13789 views
Discussion

Large signal SNR with transient noise analysis

Category: Custom IC Design

By JoHi
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updated over 9 years ago by JoHi

3 replies • 14867 views
Discussion

Run RCX Problems

Category: Custom IC Design

By rafaelon
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updated over 9 years ago by Andrew Beckett

1 replies • 13447 views
Discussion

Verilog-A 2**integer yields wrong value

Category: Custom IC Design

By AlbertoGS
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updated over 9 years ago by Andrew Beckett

1 replies • 3710 views
Discussion

ADE-XL: How to force individual result directories for each Monte Carlo point?

Category: Custom IC Design

By dontpanic
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updated over 9 years ago by Andrew Beckett

24 replies • 26920 views
Discussion

What is the difference between Id and Ids notation in result browser

Category: Custom IC Design

By syafiq
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updated over 9 years ago by Andrew Beckett

1 replies • 17758 views
Discussion

pss/qpss in the same run (alter? in ADE L?)

Category: Custom IC Design

By itos
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updated over 9 years ago by Andrew Beckett

4 replies • 2436 views
Discussion

Netlisting failed with multiple Verilog-A blocks

Category: Custom IC Design

By ywyc
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updated over 9 years ago by Andrew Beckett

1 replies • 16229 views
Discussion

ams license queuing

Category: Custom IC Design

By analogcad2
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updated over 9 years ago by Sandeep4386

5 replies • 14827 views
Discussion

Generating a current waveform in Cadence

Category: Custom IC Design

By BaaB
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updated over 9 years ago by BaaB

2 replies • 14063 views
Discussion

Transient-Noise Analysis, problem with multiple run mode

Category: Custom IC Design

By Amir0098
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updated over 9 years ago by Amir0098

2 replies • 14311 views
Discussion

Problem with HSPICE Shooting Newton (SN) AC analysis in Cadence ADE

Category: Custom IC Design

By jdp721
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updated over 9 years ago by Andrew Beckett

1 replies • 14494 views
Discussion

how could i handle a dual-path PFD+CP structure when using noise aware PLL flow?

Category: Custom IC Design

By danglanggao
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updated over 9 years ago by Andrew Beckett

5 replies • 2973 views

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