Custom IC Design

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Discussion

update a primitive property for all schematics in a library

Category: Custom IC Design

By KCjen

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updated over 10 years ago by Andrew Beckett

1 replies • 13419 views
Discussion

warnings

Category: Custom IC Design

By Sali

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updated over 10 years ago by Andrew Beckett

1 replies • 14224 views
Discussion

PLL spectre simulator settings

Category: Custom IC Design

By jeffreyprin

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updated over 10 years ago by Frank Wiedmann

2 replies • 16344 views
Discussion

dialogs come up behind other windows

Category: Custom IC Design

By danmc

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updated over 10 years ago by Andrew Beckett

3 replies • 16429 views
Discussion

Error during Montecarlo simulation

Category: Custom IC Design

By Abhilash K N

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updated over 10 years ago by Andrew Beckett

1 replies • 13935 views
Discussion

Copy an image from Cadence

Category: Custom IC Design

By zizo2012

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updated over 10 years ago by Andrew Beckett

5 replies • 15152 views
Discussion

gpdk045 drain-source breakdown voltage

Category: Custom IC Design

By JorisLambrecht

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updated over 10 years ago by JorisLambrecht

4 replies • 17443 views
Discussion

Extrapolation failed: SINGULARITY

Category: Custom IC Design

By freitas

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updated over 10 years ago by Andrew Beckett

1 replies • 14238 views
Discussion

CMOS Inverter Switching Threshold

Category: Custom IC Design

By mkza1002

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updated over 10 years ago by analogy

2 replies • 15155 views
Discussion

spectre says "The following branches form a loop of rigid branches "

Category: Custom IC Design

By eashwar g

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updated over 10 years ago by Frank Wiedmann

20 replies • 26509 views
Discussion

values of a cursor messed up

Category: Custom IC Design

By Karev11

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updated over 10 years ago by Andrew Beckett

1 replies • 13935 views
Discussion

schematic transfer between different versions

Category: Custom IC Design

By Faizan UL HAQ

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updated over 10 years ago by Andrew Beckett

3 replies • 16235 views
Discussion

Spectre simulation abortion

Category: Custom IC Design

By huadel

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updated over 10 years ago by Andrew Beckett

1 replies • 13737 views
Discussion

Generate netlist with subckt statement for top level

Category: Custom IC Design

By Octavian

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updated over 10 years ago by Matt Lanahan

12 replies • 20595 views
Discussion

failed to simulate veriloga in hspice : call to epvaHDLcgen failed

Category: Custom IC Design

By zongya

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updated over 10 years ago by zongya

2 replies • 16682 views

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