Custom IC Design

Latest Posts

Discussion

Verilog-A read file separated by delays

Category: Custom IC Design

By kennethbrun

$usertype
•
updated over 11 years ago by Andrew Beckett

12 replies • 22281 views
Discussion

Report the netlist types used in ADE XL netlists?

Category: Custom IC Design

By sram8t

$usertype
•
updated over 11 years ago by sram8t

9 replies • 15122 views
Discussion

Execution of ocean script in Cadence IC 6.1.5 and Cadence IC 5.1.41

Category: Custom IC Design

By Lings

$usertype
•
updated over 11 years ago by Andrew Beckett

5 replies • 14575 views
Discussion

Layout GXL: Flight wires not displaying

Category: Custom IC Design

By wewa

$usertype
•
updated over 11 years ago by wewa

4 replies • 16007 views
Discussion

How to execute a c programme in UNIX using SKILL

Category: Custom IC Design

By AmitBiswas

$usertype
•
updated over 11 years ago by Andrew Beckett

1 replies • 13309 views
Discussion

VerilogA models in Cadence

Category: Custom IC Design

By Sali

$usertype
•
updated over 11 years ago by Sali

12 replies • 21588 views
Discussion

LVS does not accept proper termOrder

Category: Custom IC Design

By Kabal

$usertype
•
updated over 11 years ago by Kabal

9 replies • 19410 views
Discussion

Adding Layout block from Encounter to custom design

Category: Custom IC Design

By Kabal

$usertype
•
updated over 11 years ago by Andrew Beckett

6 replies • 16303 views
Discussion

How-to edit CGSO and CGDO parameters and resimulate

Category: Custom IC Design

By cozdag

$usertype
•
updated over 11 years ago by Andrew Beckett

1 replies • 14878 views
Discussion

Parasitic extraction of standalone metal traces (IC6.1.5)

Category: Custom IC Design

By Wes8

$usertype
•
updated over 11 years ago by Andrew Beckett

1 replies • 14748 views
Discussion

How to add noise in v source?

Category: Custom IC Design

By madhusudha

$usertype
•
updated over 11 years ago by Andrew Beckett

3 replies • 28460 views
Discussion

Transient Noise Analysis | Noise File

Category: Custom IC Design

By pitter

$usertype
•
updated over 11 years ago by Andrew Beckett

3 replies • 17970 views
Discussion

Hierarchy Editor - Setting schematic view recursively within a tree

Category: Custom IC Design

By cdonovan

$usertype
•
updated over 11 years ago by cdonovan

2 replies • 2389 views
Discussion

DRC error in resistor layout

Category: Custom IC Design

By whitefan

$usertype
•
updated over 11 years ago by whitefan

1 replies • 14658 views
Discussion

Getting back source layout from gds

Category: Custom IC Design

By ImonMondal

$usertype
•
updated over 11 years ago by ImonMondal

2 replies • 13891 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.