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Custom IC Design

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  • Discussion

    HISIM-HV models

    Category: Custom IC Design

    By pejmank

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    updated over 4 years ago by Andrew Beckett

    2 replies • 11870 views
  • Discussion

    Verilog-A white_noise function returns 0 in transient noise simulation

    Category: Custom IC Design

    By threepwood06

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    updated over 4 years ago by threepwood06

    4 replies • 12653 views
  • Discussion

    Canceling out the parasitic diode in Layout

    Category: Custom IC Design

    By Hossein Eslahi

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    •

    started over 4 years ago

    0 replies • 11489 views
  • Discussion

    Current density check for layout design

    Category: Custom IC Design

    By Senan

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    •

    updated over 4 years ago by Senan

    4 replies • 14017 views
  • Discussion

    "ERROR: attempt to access a quantity that depends on the time derivative" in Verilog-A

    Category: Custom IC Design

    By rhanna

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    •

    updated over 4 years ago by Andrew Beckett

    13 replies • 5880 views
  • Discussion

    Bindkeys in ADE Explorer/Assembler

    Category: Custom IC Design

    By crossi

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    •

    updated over 4 years ago by crossi

    5 replies • 2805 views
  • Discussion

    illegal connection CAD warning message

    Category: Custom IC Design

    By Senan

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    started over 4 years ago

    0 replies • 11304 views
  • Discussion

    "ncelab: *E,CUVPOM " Errors... is invalid or has multiple connections

    Category: Custom IC Design

    By RFStuff

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    •

    updated over 4 years ago by Andrew Beckett

    1 replies • 9055 views
  • Discussion

    Issues in using a Verilog-A output as input to a Verilog-AMS block

    Category: Custom IC Design

    By RFStuff

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    updated over 4 years ago by Andrew Beckett

    2 replies • 13420 views
  • Discussion

    LVS fails "nothing in layout"

    Category: Custom IC Design

    By nicola91it

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    •

    updated over 4 years ago by Reyvandi

    4 replies • 8393 views
  • Discussion

    issue in launching Technology file manager

    Category: Custom IC Design

    By skillEater

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    updated over 4 years ago by Andrew Beckett

    4 replies • 11680 views
  • Discussion

    Define 2D parameter array in Verilog-A

    Category: Custom IC Design

    By rhanna

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    •

    updated over 4 years ago by Andrew Beckett

    3 replies • 14742 views
  • Discussion

    export and import in cadence

    Category: Custom IC Design

    By Farnaz

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    •

    updated over 4 years ago by Andrew Beckett

    2 replies • 12668 views
  • Discussion

    Declaration, Initialization and shifting real type arrays in VerilogAMS

    Category: Custom IC Design

    By RFStuff

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    •

    updated over 4 years ago by Andrew Beckett

    5 replies • 14915 views
  • Discussion

    Thermometer code

    Category: Custom IC Design

    By sidm

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    •

    updated over 4 years ago by sidm

    6 replies • 19373 views
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