Custom IC Design

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Discussion

How to get application type and/or window id from session

Category: Custom IC Design

By alexstepanov75

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updated over 3 years ago by alexstepanov75

5 replies • 3271 views
Discussion

The way to define variable correlated to ac simulation in .scs model

Category: Custom IC Design

By sjwprcker

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updated over 3 years ago by Andrew Beckett

1 replies • 8060 views
Discussion

maestro Results pane order. How to reset back to default?

Category: Custom IC Design

By Pirate King

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updated over 3 years ago by Andrew Beckett

2 replies • 9443 views
Discussion

Performing Monte-Carlo simulation with AMS

Category: Custom IC Design

By Svilen64

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updated over 3 years ago by FormerMember

4 replies • 10238 views
Discussion

Batch run simulations with different initial conditions.

Category: Custom IC Design

By skcy2001

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updated over 3 years ago by FormerMember

1 replies • 8022 views
Discussion

Grouping instances in layout

Category: Custom IC Design

By Senan

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updated over 3 years ago by Senan

2 replies • 9242 views
Discussion

Netlisting Unsuccessful for PEX Simulation in ADE/ADEXL

Category: Custom IC Design

By shbmsra12

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updated over 3 years ago by shbmsra12

4 replies • 7353 views
Discussion

Segmentation fault upon VerilogA compilation with an if condition

Category: Custom IC Design

By AAbdelRahman

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updated over 3 years ago by AAbdelRahman

4 replies • 9006 views
Discussion

Skill equivalent of "Open design in tab" in Assembler

Category: Custom IC Design

By alexstepanov75

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updated over 3 years ago by alexstepanov75

5 replies • 2068 views
Discussion

How to assign two dimensional bus notation in schematics

Category: Custom IC Design

By delgsy

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updated over 3 years ago by delgsy

2 replies • 12752 views
Discussion

How to pause a Monte-Carlo simulation run and release license

Category: Custom IC Design

By Svilen64

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updated over 3 years ago by Svilen64

13 replies • 13493 views
Discussion

Is it possible to make the log window line wrap its text?

Category: Custom IC Design

By delgsy

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updated over 3 years ago by Andrew Beckett

3 replies • 8575 views
Discussion

How to simulate portion of the circuit with pre layout models & remaining circuit with post layout models?

Category: Custom IC Design

By VenkateshTati

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updated over 3 years ago by VenkateshTati

4 replies • 2835 views
Discussion

[Verilog-A/AMS] Using a for loop to instantiate module

Category: Custom IC Design

By delgsy

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updated over 3 years ago by delgsy

4 replies • 10543 views
Discussion

[SOLVED] [Verilog-A/AMS] Instantiating verilog-ams with analog input and digital output

Category: Custom IC Design

By delgsy

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updated over 3 years ago by Andrew Beckett

1 replies • 4295 views

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