Custom IC Design

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Discussion

Virtuoso Schematic shows graphically different values than query

Category: Custom IC Design

By WRM

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updated 10 months ago by WRM

2 replies • 2746 views
Discussion

Unable to remove text labels after flattening layout pcell

Category: Custom IC Design

By Ma100B

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updated 10 months ago by Ma100B

5 replies • 3414 views
Discussion

Maestro - problem with sweeping a transistor parameter because of netlist format

Category: Custom IC Design

By frankp

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updated 10 months ago by frankp

2 replies • 922 views
Discussion

Skill function to set x- or y-axis to linear scale

Category: Custom IC Design

By TB202408221839

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started 10 months ago

0 replies • 429 views
Discussion

Merge buses when creating a symbol from SpectreText netlist

Category: Custom IC Design

By ArthurP

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started 10 months ago

0 replies • 2401 views
Discussion

Can move component only up/down or left/right in Cadence Virtuoso

Category: Custom IC Design

By NN202501183253

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updated 10 months ago by RobMan

1 replies • 1054 views
Discussion

analogLib/bsource component with complex coefficient

Category: Custom IC Design

By TommasoF

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updated 10 months ago by TommasoF

3 replies • 1087 views
Discussion

Is it possible to access design variable as parameter of systemverilog bloc

Category: Custom IC Design

By Mathieu Chene

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started 10 months ago

0 replies • 2354 views
Discussion

Issue OSSPDA with xcellium AMS sim

Category: Custom IC Design

By Binhngo1210

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started 10 months ago

0 replies • 2331 views
Discussion

Descend menu - Set default preferences

Category: Custom IC Design

By strotta

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updated 10 months ago by henker

1 replies • 543 views
Discussion

Synchronicity vs maestro view

Category: Custom IC Design

By StephanWeber

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updated 10 months ago by Andrew Beckett

1 replies • 2658 views
Discussion

Colorcoding for low cpk in Yield-View in Assembler

Category: Custom IC Design

By leok

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updated 10 months ago by StephanWeber

1 replies • 3038 views
Discussion

ADE output for conditional string from input logic combination

Category: Custom IC Design

By StephanWeber

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started 10 months ago

0 replies • 2292 views
Discussion

back annotating bussed terminal DC voltages with cdsterm in Symbol

Category: Custom IC Design

By ebecheto

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updated 10 months ago by ebecheto

4 replies • 3032 views
Discussion

Unable to run PVS Quantus extraction in cds_ff_mpt (finfet 18nm)

Category: Custom IC Design

By nikhil2798gp

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updated 10 months ago by Ganesh

6 replies • 3601 views

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