Custom IC Design

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Discussion

Remote-Host Simulation in ADE-L (or ADE Assembler) Does Not End

Category: Custom IC Design

By DrSeo

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updated over 3 years ago by DrSeo

1 replies • 10021 views
Discussion

How to run simulations in Explorer/Assembler starting from a netlist?

Category: Custom IC Design

By IceTea

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updated over 3 years ago by FormerMember

8 replies • 5215 views
Discussion

Inherited connections and VXL.....again.

Category: Custom IC Design

By kenc184

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updated over 3 years ago by kenc184

4 replies • 11327 views
Discussion

How do I set valid layers on bootup of Cadence Virtuoso XL?

Category: Custom IC Design

By dietSprunk

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updated over 3 years ago by Andrew Beckett

1 replies • 10186 views
Discussion

Any option in VLS to save one particular layer in hierarchy to a new view?

Category: Custom IC Design

By ssram

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updated over 3 years ago by Andrew Beckett

3 replies • 13776 views
Discussion

Accuracy of CROSS() function in Verilog-A

Category: Custom IC Design

By RFStuff

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updated over 3 years ago by atulkumar245

8 replies • 26707 views
Discussion

Creating a New PCELL from an existing Pcell and adding A new parameter to it

Category: Custom IC Design

By RFStuff

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updated over 3 years ago by Andrew Beckett

3 replies • 15486 views
Discussion

Creating a string expression in ADEL (or explorer) output section

Category: Custom IC Design

By Svilen64

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updated over 3 years ago by Svilen64

6 replies • 12545 views
Discussion

Non-default path to 'si.env' configuration file when calling 'si' executable from the command line to export CDL netlist from OA schematic ?

Category: Custom IC Design

By lpacher

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updated over 3 years ago by Andrew Beckett

1 replies • 1802 views
Discussion

Simulation files for Circuit Optimization App Note

Category: Custom IC Design

By delgsy

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updated over 3 years ago by Andrew Beckett

1 replies • 8723 views
Discussion

How to inspect older Assembler test setups e.g. regarding tran analysis details?

Category: Custom IC Design

By StephanWeber

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updated over 3 years ago by Andrew Beckett

1 replies • 8703 views
Discussion

Applying multi-bit VCSV files in analog virtuoso schematic

Category: Custom IC Design

By Johanny Saenz

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updated over 3 years ago by Andrew Beckett

1 replies • 9615 views
Discussion

geomOr vs. geomCat

Category: Custom IC Design

By marcelpreda

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updated over 3 years ago by Andrew Beckett

1 replies • 8823 views
Discussion

Verilog A compact modeling

Category: Custom IC Design

By atulkumar245

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started over 3 years ago

0 replies • 8641 views
Discussion

simulation not running when starting a new test simulation

Category: Custom IC Design

By dileeps

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started over 3 years ago

0 replies • 9722 views

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