Custom IC Design

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Error doing in Local Optimization in ADE Assembler

Category: Custom IC Design

By Bakr Abdelgaliel

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updated 7 months ago by Bakr Abdelgaliel

2 replies • 2061 views
Discussion

spectre assert

Category: Custom IC Design

By Joe Mellon

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updated 7 months ago by Joe Mellon

2 replies • 2201 views
Discussion

Follow Up Discussion on Maestro can't save current with "WARNING (ADE-1063): The output with same signal '***' is already defined."

Category: Custom IC Design

By Kelsey Reed

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updated 7 months ago by Kelsey Reed

1 replies • 462 views
Discussion

How do I set default layout view for EM/IR data layout analysis Lib/Cell/View

Category: Custom IC Design

By BillH314

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started 7 months ago

0 replies • 291 views
Discussion

The drain and source is different direction in pex with different fingers of the same mos

Category: Custom IC Design

By dogman4

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updated 7 months ago by Andrew Beckett

1 replies • 1991 views
Discussion

The current direction is different after simulation with different fingers of the same mos

Category: Custom IC Design

By dogman4

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updated 7 months ago by dogman4

3 replies • 2343 views
Discussion

Generate steamOut.map for Innovus GDS export in Virtuoso?

Category: Custom IC Design

By Gurjot Singh

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updated 7 months ago by Andrew Beckett

1 replies • 2213 views
Discussion

information about (description of) gsclib045 components?

Category: Custom IC Design

By GS202507021424

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updated 7 months ago by GS202507021424

2 replies • 2265 views
Discussion

VIVA: Change color/disable highlighting around current (sub-)window

Category: Custom IC Design

By dontpanic

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updated 7 months ago by dontpanic

6 replies • 1168 views
Discussion

Problems with genvar and nested for loops in verilog-A after updating the Cadence tools

Category: Custom IC Design

By Esmee Tackx

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started 8 months ago

0 replies • 2083 views
Discussion

Latency to Connect License server

Category: Custom IC Design

By Tarique mohd

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updated 8 months ago by Saloni Chhabra

3 replies • 2578 views
Discussion

Parasitic Extraction Failure in Quantus - Assura

Category: Custom IC Design

By MK202507103018

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started 8 months ago

0 replies • 300 views
Discussion

Netlisting 'config' view with SPICE source file... CDF parameter m= on symbol is not printed in netlist instance call

Category: Custom IC Design

By JeffBeck

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updated 8 months ago by JeffBeck

2 replies • 927 views
Discussion

pxf or pac sampled Explanation

Category: Custom IC Design

By Patrick Chang

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started 8 months ago

0 replies • 1934 views
Discussion

calcVal function works during the simulation, but fails after initiating re-evaluation

Category: Custom IC Design

By A1vis

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updated 8 months ago by A1vis

8 replies • 3806 views

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