Custom IC Design

Latest Posts

Discussion

Can't import techfile into abstract (IC6.1.4)

Category: Custom IC Design

By dura

$usertype
•
updated over 13 years ago by Aritra

2 replies • 1080 views
Discussion

Translating IC5 libaries to IC6

Category: Custom IC Design

By DineshBabu

$usertype
•
updated over 13 years ago by DineshBabu

2 replies • 15920 views
Discussion

how to recover a locked simulation on the Cadence server?

Category: Custom IC Design

By sohaibafridi

$usertype
•
updated over 13 years ago by Quek

11 replies • 6378 views
Discussion

getting rid of little informational text on mpps

Category: Custom IC Design

By linbo

$usertype
•
updated over 13 years ago by linbo

3 replies • 13528 views
Discussion

Writing simulation data into a file after running

Category: Custom IC Design

By Medya

$usertype
•
updated over 13 years ago by Andrew Beckett

1 replies • 13104 views
Discussion

ADE XL: default x axis for plots

Category: Custom IC Design

By keble6

$usertype
•
updated over 13 years ago by keble6

2 replies • 13924 views
Discussion

Parameterized VHDL using generics and ADE-AMS simulation

Category: Custom IC Design

By lperktold

$usertype
•
started over 13 years ago

0 replies • 13452 views
Discussion

get first pole from PZ analysis

Category: Custom IC Design

By Rainer123

$usertype
•
updated over 13 years ago by Rainer123

4 replies • 13763 views
Discussion

Generate Clones does not work

Category: Custom IC Design

By tyanata

$usertype
•
updated over 13 years ago by tyanata

2 replies • 14005 views
Discussion

DC Match Over Corners

Category: Custom IC Design

By BVT1

$usertype
•
started over 13 years ago

0 replies • 13212 views
Discussion

How to translate netlist with subcircuits into top-level subcircuit?

Category: Custom IC Design

By TiNat

$usertype
•
updated over 13 years ago by skillUser

1 replies • 6464 views
Discussion

Assura LVS error (cell expanded), need help debugging the error !!

Category: Custom IC Design

By SivaChaitanya

$usertype
•
updated over 13 years ago by SivaChaitanya

1 replies • 16822 views
Discussion

Howto read port currents when having multi-terminal bus ports in VerilogA ?

Category: Custom IC Design

By Herge

$usertype
•
updated over 13 years ago by Herge

6 replies • 15770 views
Discussion

How to debug VerilogA compilation when code seems to check clean but simulation aborts when compiling ?

Category: Custom IC Design

By Herge

$usertype
•
updated over 13 years ago by Herge

3 replies • 15129 views
Discussion

montecarlo simulations beetween Wmin and Wmax for mos transistors

Category: Custom IC Design

By inessadm

$usertype
•
updated over 13 years ago by inessadm

2 replies • 13523 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.