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Custom IC Design

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  • Discussion

    Assembler maestro default jobs in cleaningup state for many hours

    Category: Custom IC Design

    By sidm sidm

    •

    updated over 1 year ago by Andrew Beckett

    3 replies • 3404 views
  • Discussion

    how to use Connect by Name Highlighting to highlight only one net?

    Category: Custom IC Design

    By simonwishes simonwishes

    •

    updated over 1 year ago by simonwishes

    2 replies • 3465 views
  • Discussion

    Need help in extracting a SPICE from a layout

    Category: Custom IC Design

    By gaddan14 gaddan14

    •

    updated over 1 year ago by RobMan

    1 replies • 3341 views
  • Discussion

    ADE didn't generate the correct when using spf through config

    Category: Custom IC Design

    By CambridgeLv CambridgeLv

    •

    updated over 1 year ago by CambridgeLv

    4 replies • 2148 views
  • Discussion

    The env variable to set schematic find zoom

    Category: Custom IC Design

    By sjwprcker sjwprcker

    •

    updated over 1 year ago by Andrew Beckett

    3 replies • 3483 views
  • Discussion

    Modifying Model Groups based on Environmental Variable

    Category: Custom IC Design

    By jdsherman jdsherman

    •

    updated over 1 year ago by Andrew Beckett

    1 replies • 3062 views
  • Discussion

    how to stop virtuoso opening the schematic cellview when I open the layout view?

    Category: Custom IC Design

    By BS202407197848 BS202407197848

    •

    updated over 1 year ago by Andrew Beckett

    1 replies • 3536 views
  • Discussion

    [liberate] FAILED TO GET MOS MODEL FOR 'XMP32_0'!

    Category: Custom IC Design

    By sherryshe sherryshe

    •

    updated over 1 year ago by Guangjun Cao

    3 replies • 982 views
  • Discussion

    top level parameter transfer to lower level verilog-A block

    Category: Custom IC Design

    By MikeA MikeA

    •

    started over 1 year ago

    0 replies • 3189 views
  • Discussion

    How to write an equation to measure pk-to-pk jitter from eye diagrams

    Category: Custom IC Design

    By paramx paramx

    •

    updated over 1 year ago by paramx

    4 replies • 4578 views
  • Discussion

    Issue with Spectre reliability analysis (negative aging)

    Category: Custom IC Design

    By Amel Amel

    •

    updated over 1 year ago by Andrew Beckett

    1 replies • 3252 views
  • Discussion

    virtuoso schematic replace function

    Category: Custom IC Design

    By liangqunshan liangqunshan

    •

    updated over 1 year ago by liangqunshan

    2 replies • 3614 views
  • Discussion

    BlackBox with Assura LVS

    Category: Custom IC Design

    By SteS93 SteS93

    •

    updated over 1 year ago by SteS93

    1 replies • 4223 views
  • Discussion

    Switching from voltage source to high impedance port in VerilogA: Convergence problem

    Category: Custom IC Design

    By mohthi3 mohthi3

    •

    started over 1 year ago

    0 replies • 2930 views
  • Discussion

    How to decrease the capacitance of charging and discharging at the MSB of current steering DAC

    Category: Custom IC Design

    By Phd SA88 Phd SA88

    •

    updated over 1 year ago by Andrew Beckett

    2 replies • 3253 views
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