Custom IC Design

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Maestro - Elapsed time to results

Category: Custom IC Design

By JeyJey

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updated over 3 years ago by FormerMember

11 replies • 5718 views
Discussion

illegal weak connection warning issue

Category: Custom IC Design

By Senan

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updated over 3 years ago by Andrew Beckett

1 replies • 12920 views
Discussion

question ： standard cell symbol import to virtuoso

Category: Custom IC Design

By jackkong

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updated over 3 years ago by jackkong

10 replies • 13296 views
Discussion

$analog_node_alias() usage with vector nets

Category: Custom IC Design

By dtodorov

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updated over 3 years ago by dtodorov

1 replies • 9468 views
Discussion

Exporting device component values and operating conditions into a table in Virtuoso

Category: Custom IC Design

By sidm

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updated over 3 years ago by FormerMember

3 replies • 10429 views
Discussion

constrain the memory use in cadence

Category: Custom IC Design

By huadel

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updated over 3 years ago by SC6789

3 replies • 16485 views
Discussion

Control flow when a return from an expression is nil

Category: Custom IC Design

By delgsy

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updated over 3 years ago by FormerMember

4 replies • 11480 views
Discussion

Any efficient way to do calibration using calcVal and MonteCarlo for tripple nested loop?

Category: Custom IC Design

By delgsy

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updated over 3 years ago by delgsy

2 replies • 10072 views
Discussion

DC Convergence Problem When Simulating a Post-Layout r_c and r_c_cc Extraction

Category: Custom IC Design

By shbmsra12

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updated over 3 years ago by Andrew Beckett

5 replies • 12117 views
Discussion

xi0.m1: Effective length is less than or equal to zero?? newbie in cadence!

Category: Custom IC Design

By archive

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updated over 3 years ago by Andrew Beckett

4 replies • 16812 views
Discussion

leaf cell issue with using diffstbprobe

Category: Custom IC Design

By kenc184

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updated over 3 years ago by kenc184

2 replies • 10819 views
Discussion

Saving the image of many output signals in Cadence Virtuoso

Category: Custom IC Design

By Senan

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updated over 3 years ago by Senan

2 replies • 10328 views
Discussion

Is it normal for DeCap to get 0 value leakage power when running liberate?

Category: Custom IC Design

By sherryshe

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updated over 3 years ago by Guangjun Cao

1 replies • 9685 views
Discussion

How to backannotate Monte-Carlo DCOP simulation results to schematic

Category: Custom IC Design

By delgsy

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updated over 3 years ago by delgsy

2 replies • 9930 views
Discussion

Statistical file for Monte Carlo analysis

Category: Custom IC Design

By Hemaresearch

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updated over 3 years ago by Andrew Beckett

3 replies • 11537 views

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