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Custom IC Design

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  • Discussion

    Which simulation tools are supported for Voltus-XFi within Virtuoso environment?

    Category: Custom IC Design

    By JY202510312553

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    started 4 days ago

    0 replies • 69 views
  • Discussion

    TSMC PDK Inductor Finder

    Category: Custom IC Design

    By nqthang

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    •

    started 4 days ago

    0 replies • 119 views
  • Discussion

    Fundamental question on edge phase noise from sampled PNOISE

    Category: Custom IC Design

    By Yuto Lau

    $usertype

    •

    updated 5 days ago by Yuto Lau

    6 replies • 445 views
  • Discussion

    PWM block gain simulation using pss

    Category: Custom IC Design

    By TH202510293247

    $usertype

    •

    started 5 days ago

    0 replies • 92 views
  • Discussion

    Cadence Virtuoso IC6.1.8 - Layout GXL Automatic Placement

    Category: Custom IC Design

    By hoangtn3702

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    •

    started 6 days ago

    0 replies • 106 views
  • Discussion

    wait a long time to have results updated

    Category: Custom IC Design

    By sjwprcssw

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    •

    started 7 days ago

    0 replies • 154 views
  • Discussion

    SOA analysis in cadence virtuoso

    Category: Custom IC Design

    By TUKA

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    •

    started 8 days ago

    0 replies • 141 views
  • Discussion

    Strategy for Accelerating Full-Chip AMS Simulation with Multi-Rate Clocks (1kHz / 100MHz)

    Category: Custom IC Design

    By HY202510149941

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    •

    updated 8 days ago by Alonso Schmidt

    1 replies • 310 views
  • Discussion

    Buses in spectreText when creating symbol

    Category: Custom IC Design

    By MC20250412421

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    •

    updated 9 days ago by MC20250412421

    2 replies • 310 views
  • Discussion

    Does Cadence provide a standard Python API for tool automation?

    Category: Custom IC Design

    By WM20250906725

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    •

    updated 12 days ago by Andrew Beckett

    5 replies • 2208 views
  • Discussion

    Issue with Skywater 130 Monte Carlo Mismatch Analysis

    Category: Custom IC Design

    By VLSI lab IITB

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    •

    updated 13 days ago by VLSI lab IITB

    2 replies • 438 views
  • Discussion

    Issue with the ADE Explorer/Assembler simulator

    Category: Custom IC Design

    By GL202502244954

    $usertype

    •

    started 13 days ago

    0 replies • 153 views
  • Discussion

    Date/time (or $system) in verilogA

    Category: Custom IC Design

    By leok

    $usertype

    •

    updated 15 days ago by leok

    2 replies • 257 views
  • Discussion

    quantus parasitic extraction vs. SKY130 PDK

    Category: Custom IC Design

    By GS202507021424

    $usertype

    •

    updated 17 days ago by Andrew Beckett

    2 replies • 1308 views
  • Discussion

    Quantus Error – Sky130 qrcTechFile not recognized as valid technology file

    Category: Custom IC Design

    By RK202509013321

    $usertype

    •

    updated 17 days ago by Andrew Beckett

    1 replies • 466 views
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