Custom IC Design

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Discussion

CCVS in subckt probing one level up?

Category: Custom IC Design

By drdanmc

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updated over 8 years ago by drdanmc

2 replies • 14237 views
Discussion

very long bit pattern for vbit source

Category: Custom IC Design

By Zitty

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updated over 8 years ago by Andrew Beckett

13 replies • 36930 views
Discussion

virtuoso won't start -- core dumps

Category: Custom IC Design

By KKimber

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updated over 8 years ago by KKimber

2 replies • 3426 views
Discussion

Physical verification system menu is not working properly

Category: Custom IC Design

By anandmohan

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updated over 8 years ago by Marben

4 replies • 15500 views
Discussion

How do I override irunArgs being set by the ADE state when using runams?

Category: Custom IC Design

By feory

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updated over 8 years ago by Adam Daniels

3 replies • 14522 views
Discussion

unable to load .sdb file

Category: Custom IC Design

By syafiq

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updated over 8 years ago by Andrew Beckett

3 replies • 15820 views
Discussion

How to know that ALL MOS are in saturaion region by running ocean script?

Category: Custom IC Design

By MOSMOS

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updated over 8 years ago by Andrew Beckett

10 replies • 17682 views
Discussion

APS, Multi-threading, High-Performance Simulation...

Category: Custom IC Design

By aditeman

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updated over 8 years ago by lartola

11 replies • 30984 views
Discussion

LVS without schematic

Category: Custom IC Design

By Julien Terrier

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updated over 8 years ago by Andrew Beckett

8 replies • 18555 views
Discussion

cds_get_analog_value for inherited connection

Category: Custom IC Design

By nthoangga

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started over 8 years ago

0 replies • 13219 views
Discussion

Passing different CDF parameters values to instance arrays

Category: Custom IC Design

By pacikk

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updated over 8 years ago by pacikk

2 replies • 14820 views
Discussion

Any way to format the print statement in spice?

Category: Custom IC Design

By RK56

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updated over 8 years ago by Andrew Beckett

3 replies • 15977 views
Discussion

Help in HB Simulation in an autonomous circuit with driving signal input.

Category: Custom IC Design

By Abdhkamal

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updated over 8 years ago by Andrew Beckett

1 replies • 14307 views
Discussion

Solved: binary counter in VerilogA with programmable stepsize

Category: Custom IC Design

By Clidre

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updated over 8 years ago by vijaykpd

4 replies • 25881 views
Discussion

RelXpert Error with intermediate file input.p1

Category: Custom IC Design

By PatriciaG

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updated over 8 years ago by Andrew Beckett

1 replies • 13492 views

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