Custom IC Design

Latest Posts

Discussion

How to greate guard ring for Cadence GPDK FinFet?

Category: Custom IC Design

By hesdeadJim
•
updated 1 month ago by hesdeadJim

2 replies • 582 views
Discussion

ADE ViVA Plotting Template: Where is it stored and how to edit?

Category: Custom IC Design

By StephanWeber
•
updated 1 month ago by StephanWeber

2 replies • 577 views
Discussion

How to load viaGetViaOptions Function inside PCELL

Category: Custom IC Design

By Esteban Saavedra
•
updated 1 month ago by Andrew Beckett

4 replies • 616 views
Discussion

Any analogue or mixed signal Cadence FinFet layouts to share?

Category: Custom IC Design

By hesdeadJim
•
started 1 month ago

0 replies • 386 views
Discussion

verilog Syntax errors not highlighted in text editor

Category: Custom IC Design

By JavierC
•
updated 1 month ago by JavierC

6 replies • 885 views
Discussion

Loading *WARNING* Connection to MACHINE failed. Connection refused

Category: Custom IC Design

By hesdeadJim
•
updated 1 month ago by hesdeadJim

4 replies • 594 views
Discussion

Any major difference between Cadence Advanced Node GPDK v1.0 and v1.1 release?

Category: Custom IC Design

By hesdeadJim
•
updated 1 month ago by hesdeadJim

1 replies • 500 views
Discussion

best way to integrate different calibre extraction corners to virtuoso ADE

Category: Custom IC Design

By micipici
•
updated 1 month ago by Andrew Beckett

1 replies • 469 views
Discussion

Distributed simulations

Category: Custom IC Design

By OPump
•
updated 1 month ago by OPump

1 replies • 471 views
Discussion

Automatic routing --> All nets in Layout GXL of Cadence Virtuoso

Category: Custom IC Design

By HN20250717689
•
started 1 month ago

0 replies • 210 views
Discussion

How to plot a histogram of a relative error in a Monte Carlo analysis?

Category: Custom IC Design

By DomiHammerfall
•
updated 1 month ago by DomiHammerfall

3 replies • 650 views
Discussion

Unable to run Monte-Carlo simulation on ADE-XL

Category: Custom IC Design

By rtyuy
•
updated 1 month ago by rtyuy

32 replies • 2730 views
Discussion

Error doing in Local Optimization in ADE Assembler

Category: Custom IC Design

By Bakr Abdelgaliel
•
updated 1 month ago by Bakr Abdelgaliel

2 replies • 540 views
Discussion

spectre assert

Category: Custom IC Design

By Joe Mellon
•
updated 1 month ago by Joe Mellon

2 replies • 645 views
Discussion

Follow Up Discussion on Maestro can't save current with "WARNING (ADE-1063): The output with same signal '***' is already defined."

Category: Custom IC Design

By Kelsey Reed
•
updated 1 month ago by Kelsey Reed

1 replies • 267 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.