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Custom IC Design

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  • Discussion

    modeling device using Verilog-A and having convergence problems

    Category: Custom IC Design

    By funfet

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    updated over 8 years ago by Andrew Beckett

    1 replies • 14651 views
  • Discussion

    ADE-L: How to specify "options statements" for Spectre?

    Category: Custom IC Design

    By dontpanic

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    •

    updated over 8 years ago by dontpanic

    3 replies • 9675 views
  • Discussion

    Virtuoso Layout L: Show/remove hidden/old (metal) layers

    Category: Custom IC Design

    By itos

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    updated over 8 years ago by itos

    4 replies • 4427 views
  • Discussion

    Confusion about DRC / LVS / Parasitic extraction tools

    Category: Custom IC Design

    By manudupouy

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    updated over 8 years ago by manudupouy

    2 replies • 15720 views
  • Discussion

    ADE XL and virtuoso -nograph not working

    Category: Custom IC Design

    By tarakda

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    updated over 8 years ago by Andrew Beckett

    1 replies • 2338 views
  • Discussion

    Transient Simulation of AMS gives convergence error

    Category: Custom IC Design

    By ashrafSazid

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    •

    updated over 8 years ago by Andrew Beckett

    1 replies • 15249 views
  • Discussion

    Create Vias: shapes, drawn areas

    Category: Custom IC Design

    By JWHoll

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    •

    updated over 8 years ago by Quek

    1 replies • 15378 views
  • Discussion

    Oversampling clock and data recovery for SerDes communication

    Category: Custom IC Design

    By bitan1990

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    •

    started over 8 years ago

    0 replies • 13341 views
  • Discussion

    Modify the resistivity of M1

    Category: Custom IC Design

    By samer1

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    updated over 8 years ago by samer1

    8 replies • 14898 views
  • Discussion

    what is the use of data.dm and constraint in each design directory?

    Category: Custom IC Design

    By Qilong

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    •

    updated over 8 years ago by Andrew Beckett

    1 replies • 27460 views
  • Discussion

    VIVA: how to disable automatic displaying of variables when hovering over trace names?

    Category: Custom IC Design

    By dontpanic

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    updated over 8 years ago by dontpanic

    4 replies • 13878 views
  • Discussion

    Change a technology library into a design library

    Category: Custom IC Design

    By Qilong

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    •

    updated over 8 years ago by Qilong

    2 replies • 18520 views
  • Discussion

    how to find total capcitance of mosfet(pmos or nmos)?

    Category: Custom IC Design

    By pavan261995

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    •

    updated over 8 years ago by Andrew Beckett

    1 replies • 931 views
  • Discussion

    anaName in OCEAN analysis not working

    Category: Custom IC Design

    By leok

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    •

    updated over 8 years ago by leok

    2 replies • 13318 views
  • Discussion

    QRC extraction problem

    Category: Custom IC Design

    By umais

    $usertype

    •

    updated over 8 years ago by Andrew Beckett

    3 replies • 14957 views
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