Custom IC Design

Latest Posts

Discussion

Guidelines for the Custom IC Design Forum

Category: Custom IC Design

By Andrew Beckett

$usertype
•
started over 14 years ago

0 replies • 31494 views
Discussion

Problems with Virtuoso ADE Explorer

Category: Custom IC Design

By FZ20251125769

$usertype
•
started 3 hours ago

0 replies • 22 views
Discussion

Two-Tone Harmonic Balance Noise Settings: "Relative Harmonic" and "Reference Side-Band"

Category: Custom IC Design

By YX202508199356

$usertype
•
updated 7 hours ago by YX202508199356

5 replies • 768 views
Discussion

Standard Deviation Summary in Monte Carlo Simulations Across Multiple Corners

Category: Custom IC Design

By alho1

$usertype
•
updated 14 hours ago by alho1

3 replies • 190 views
Discussion

significant digits in ADE assembler output expressions

Category: Custom IC Design

By an wx

$usertype
•
updated 2 days ago by Andrew Beckett

4 replies • 498 views
Discussion

How to set add. Spectre MC options in Assember GUI?

Category: Custom IC Design

By StephanWeber

$usertype
•
updated 3 days ago by Andrew Beckett

3 replies • 306 views
Discussion

Transient noise contribution works in spectre but failed in APS.

Category: Custom IC Design

By zuiying

$usertype
•
started 4 days ago

0 replies • 170 views
Discussion

Specifying variable as a parametric sweep in ADE Explorer (when the parametric weep involves another variable)

Category: Custom IC Design

By msharma

$usertype
•
updated 6 days ago by Andrew Beckett

1 replies • 280 views
Discussion

Getting more data after MC run directly in the Results table?

Category: Custom IC Design

By StephanWeber

$usertype
•
updated 6 days ago by Andrew Beckett

18 replies • 1363 views
Discussion

Wildcard '*' does not match any net in spectre save statement

Category: Custom IC Design

By msharma

$usertype
•
updated 6 days ago by msharma

4 replies • 403 views
Discussion

$fscanf and $fget do not work when any portion of Verilog-A file is encrypted

Category: Custom IC Design

By ConradJ

$usertype
•
updated 7 days ago by ConradJ

2 replies • 317 views
Discussion

ahdlvar not saved although saveahdlvars=all is set

Category: Custom IC Design

By StephanWeber

$usertype
•
updated 7 days ago by StephanWeber

2 replies • 271 views
Discussion

Failing to extract parasitics from layout - capgen file is missing

Category: Custom IC Design

By EG202602196052

$usertype
•
started 11 days ago

0 replies • 207 views
Discussion

Very Basic Wire naming question

Category: Custom IC Design

By HL20260227511

$usertype
•
updated 11 days ago by Andrew Beckett

1 replies • 330 views
Discussion

get the difference between two wave forms after parametric sweep.

Category: Custom IC Design

By Svilen64

$usertype
•
updated 13 days ago by Svilen64

5 replies • 534 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.