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Custom IC Design

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  • Discussion

    running aging simulation with different bias voltage and temp over time

    Category: Custom IC Design

    By Nasser Arif

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    updated over 7 years ago by Andrew Beckett

    3 replies • 14260 views
  • Discussion

    Schematic Pcell : internal node probing

    Category: Custom IC Design

    By mihirDesai

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    •

    updated over 7 years ago by Andrew Beckett

    3 replies • 15046 views
  • Discussion

    layout of MIMCAPS_MM capacitor in virtuoso 6.1.5

    Category: Custom IC Design

    By pratibhads2805

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    •

    updated over 7 years ago by Andrew Beckett

    6 replies • 22085 views
  • Discussion

    Is there the ability to check in an ADE Assembler license outside of the License manager?

    Category: Custom IC Design

    By brianjreed

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    •

    updated over 7 years ago by brianjreed

    2 replies • 14208 views
  • Discussion

    License Mistake

    Category: Custom IC Design

    By Nguyen Ngo

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    •

    updated over 7 years ago by Nguyen Ngo

    2 replies • 14328 views
  • Discussion

    Error in layout extraction

    Category: Custom IC Design

    By amnaggar

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    •

    updated over 7 years ago by amnaggar

    2 replies • 14335 views
  • Discussion

    VIVA-XL – How to differentiate same signal waves from different db’s

    Category: Custom IC Design

    By DHOFF

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    •

    started over 7 years ago

    0 replies • 677 views
  • Discussion

    ADE-XL - How to make use of licenses more efficient?

    Category: Custom IC Design

    By Pedro73

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    updated over 7 years ago by Frank Wiedmann

    1 replies • 1274 views
  • Discussion

    how to sweep an equation which is formed using variables?

    Category: Custom IC Design

    By CKAITHANYA

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    •

    updated over 7 years ago by Andrew Beckett

    3 replies • 14174 views
  • Discussion

    AMS simulation on a synthesized netlists --- NO sim result

    Category: Custom IC Design

    By manpmanp

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    updated over 7 years ago by Saloni Chhabra

    1 replies • 1765 views
  • Discussion

    Evaluate expression only after all parametric simulations are finished

    Category: Custom IC Design

    By Emiel

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    updated over 7 years ago by Emiel

    2 replies • 15140 views
  • Discussion

    Printing to a file using fprintf

    Category: Custom IC Design

    By ajitg

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    •

    updated over 7 years ago by Andrew Beckett

    1 replies • 13942 views
  • Discussion

    Cadence issue on CentOS6.7

    Category: Custom IC Design

    By Arafat01

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    •

    updated over 7 years ago by Andrew Beckett

    6 replies • 18887 views
  • Discussion

    How to change routing configuration in Power Routing Options form in Virtuoso XL

    Category: Custom IC Design

    By RoseRivera

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    •

    started over 7 years ago

    0 replies • 540 views
  • Discussion

    access signals through hierarchy in schematic

    Category: Custom IC Design

    By DavidLou

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    •

    updated over 7 years ago by DavidLou

    2 replies • 15263 views
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