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Custom IC Design

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  • Discussion

    Back and forward history buttons in Schematic Editor clearing probed nets?

    Category: Custom IC Design

    By ES20241003727 ES20241003727

    •

    updated 6 months ago by Andrew Beckett

    2 replies • 1734 views
  • Discussion

    Enabling disk-space-check via .cdsinit

    Category: Custom IC Design

    By HoWei HoWei

    •

    started 6 months ago

    0 replies • 1472 views
  • Discussion

    Installscape issue on Rocky linux8/9 and Almalinux 9

    Category: Custom IC Design

    By CB202409064221 CB202409064221

    •

    updated 7 months ago by CB202409064221

    3 replies • 1285 views
  • Discussion

    Virtuoso Schematic shows graphically different values than query

    Category: Custom IC Design

    By WRM WRM

    •

    updated 7 months ago by WRM

    2 replies • 1879 views
  • Discussion

    Unable to remove text labels after flattening layout pcell

    Category: Custom IC Design

    By Ma100B Ma100B

    •

    updated 7 months ago by Ma100B

    5 replies • 2378 views
  • Discussion

    Maestro - problem with sweeping a transistor parameter because of netlist format

    Category: Custom IC Design

    By frankp frankp

    •

    updated 7 months ago by frankp

    2 replies • 666 views
  • Discussion

    Skill function to set x- or y-axis to linear scale

    Category: Custom IC Design

    By TB202408221839 TB202408221839

    •

    started 7 months ago

    0 replies • 337 views
  • Discussion

    Merge buses when creating a symbol from SpectreText netlist

    Category: Custom IC Design

    By ArthurP ArthurP

    •

    started 7 months ago

    0 replies • 1560 views
  • Discussion

    Can move component only up/down or left/right in Cadence Virtuoso

    Category: Custom IC Design

    By NN202501183253 NN202501183253

    •

    updated 7 months ago by RobMan

    1 replies • 697 views
  • Discussion

    analogLib/bsource component with complex coefficient

    Category: Custom IC Design

    By TommasoF TommasoF

    •

    updated 7 months ago by TommasoF

    3 replies • 754 views
  • Discussion

    Is it possible to access design variable as parameter of systemverilog bloc

    Category: Custom IC Design

    By Mathieu Chene Mathieu Chene

    •

    started 7 months ago

    0 replies • 1577 views
  • Discussion

    Issue OSSPDA with xcellium AMS sim

    Category: Custom IC Design

    By Binhngo1210 Binhngo1210

    •

    started 7 months ago

    0 replies • 1576 views
  • Discussion

    Descend menu - Set default preferences

    Category: Custom IC Design

    By strotta strotta

    •

    updated 7 months ago by henker

    1 replies • 425 views
  • Discussion

    Synchronicity vs maestro view

    Category: Custom IC Design

    By StephanWeber StephanWeber

    •

    updated 7 months ago by Andrew Beckett

    1 replies • 1774 views
  • Discussion

    Colorcoding for low cpk in Yield-View in Assembler

    Category: Custom IC Design

    By leok leok

    •

    updated 7 months ago by StephanWeber

    1 replies • 2263 views
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