Custom IC Design

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Rerun History in Assembler with more points enabled while re-using previous results?

Category: Custom IC Design

By david1110

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updated over 2 years ago by david1110

5 replies • 8484 views
Discussion

Cannot Install cadence IC618 on rhel 9

Category: Custom IC Design

By Aswin98

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updated over 2 years ago by Andrew Beckett

4 replies • 13515 views
Discussion

calcVal() works fine over corners but not when variable swept

Category: Custom IC Design

By Pirate King

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updated over 2 years ago by Andrew Beckett

4 replies • 7826 views
Discussion

PSS for PLL loop

Category: Custom IC Design

By RaghavendraN

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updated over 2 years ago by Andrew Beckett

5 replies • 9857 views
Discussion

XPM file to layout or symbol view

Category: Custom IC Design

By Larry Allen

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updated over 2 years ago by Andrew Beckett

2 replies • 6463 views
Discussion

Virtuoso Schematic L "spider" effect

Category: Custom IC Design

By CSCNalu

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updated over 2 years ago by ShawnLogan

3 replies • 1289 views
Discussion

Is it possible when schematic changes in virtuso can I get some alarm or alert?

Category: Custom IC Design

By shane park

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updated over 2 years ago by shane park

2 replies • 6475 views
Discussion

Check VCO oscillating in transient and PSS

Category: Custom IC Design

By lswei1984

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updated over 2 years ago by ShawnLogan

1 replies • 7057 views
Discussion

Noise Summary per Instance

Category: Custom IC Design

By illaoi

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updated over 2 years ago by Andrew Beckett

5 replies • 8671 views
Discussion

NO DC solution found(No convergence) when use ADEXL,but use ADEL is right.

Category: Custom IC Design

By SpiceHusky

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updated over 2 years ago by Andrew Beckett

3 replies • 2095 views
Discussion

Spectre warning: there are some nodes and instances from the netlist topology check.

Category: Custom IC Design

By ppptt

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updated over 2 years ago by Andrew Beckett

1 replies • 7240 views
Discussion

PVS fails with version `GLIBCXX_3.4.26' not found

Category: Custom IC Design

By thspaet

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updated over 2 years ago by thspaet

3 replies • 3384 views
Discussion

setting cell's view in config as dynamic parameter

Category: Custom IC Design

By sjwprcker

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updated over 2 years ago by sjwprcker

2 replies • 1456 views
Discussion

BJT models HiCUM (bht)

Category: Custom IC Design

By sidm

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updated over 2 years ago by sidm

6 replies • 8513 views
Discussion

DRC check and LVS check has no error but still seeing the layer error?

Category: Custom IC Design

By Vishesh Gupta

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updated over 2 years ago by Andrew Beckett

1 replies • 6451 views

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