Custom IC Design

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Schematic Editor: Make cell EDITABLE automatically

Category: Custom IC Design

By NiallDuncan

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updated over 11 years ago by NiallDuncan

2 replies • 16258 views
Discussion

VerilogA: report DC voltage

Category: Custom IC Design

By Frank Opteynde

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updated over 11 years ago by Andrew Beckett

1 replies • 14099 views
Discussion

Error in Calc: expression evaluation failed

Category: Custom IC Design

By Vi Muthukumar

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updated over 11 years ago by Vi Muthukumar

11 replies • 26437 views
Discussion

ocean XL

Category: Custom IC Design

By analogdesign

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updated over 11 years ago by analogdesign

14 replies • 17000 views
Discussion

ASSURA 4.1 Supported Platform?

Category: Custom IC Design

By emax00

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updated over 11 years ago by Andrew Beckett

1 replies • 13215 views
Discussion

Interactive verilogA models in Spectre

Category: Custom IC Design

By Sali

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updated over 11 years ago by Sali

2 replies • 13283 views
Discussion

How to create a final netlist from ADE-XL with global variables using Skill?

Category: Custom IC Design

By adeuser777

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updated over 11 years ago by sram8t

7 replies • 17236 views
Discussion

How to Queue for a Virtuoso Schematic Editor License

Category: Custom IC Design

By nbyrne

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updated over 11 years ago by Andrew Beckett

4 replies • 14728 views
Discussion

Installing and setting up PVS10.1.2 on IC6.15

Category: Custom IC Design

By Alex Vasjanov

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updated over 11 years ago by Andrew Beckett

1 replies • 14662 views
Discussion

waveform processing question in Virtuoso ViVA

Category: Custom IC Design

By apple419

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updated over 11 years ago by Tawna

4 replies • 15341 views
Discussion

Wierd selection option

Category: Custom IC Design

By alpine

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updated over 11 years ago by alpine

2 replies • 12958 views
Discussion

finding usage/references/instances of a cell in same/other libraries Virtuoso IC6.1.4.500.12

Category: Custom IC Design

By tdtg

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updated over 11 years ago by Andrew Beckett

2 replies • 3853 views
Discussion

Xdefault for LSW menu text

Category: Custom IC Design

By danmc

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updated over 11 years ago by danmc

4 replies • 13964 views
Discussion

Verilog-A read file separated by delays

Category: Custom IC Design

By kennethbrun

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updated over 11 years ago by Andrew Beckett

12 replies • 22229 views
Discussion

Report the netlist types used in ADE XL netlists?

Category: Custom IC Design

By sram8t

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updated over 11 years ago by sram8t

9 replies • 15095 views

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