Custom IC Design

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Installscape issue on Rocky linux8/9 and Almalinux 9

Category: Custom IC Design

By CB202409064221

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updated over 1 year ago by CB202409064221

3 replies • 2158 views
Discussion

Virtuoso Schematic shows graphically different values than query

Category: Custom IC Design

By WRM

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updated over 1 year ago by WRM

2 replies • 3106 views
Discussion

Unable to remove text labels after flattening layout pcell

Category: Custom IC Design

By Ma100B

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updated over 1 year ago by Ma100B

5 replies • 3804 views
Discussion

Maestro - problem with sweeping a transistor parameter because of netlist format

Category: Custom IC Design

By frankp

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updated over 1 year ago by frankp

2 replies • 1058 views
Discussion

Skill function to set x- or y-axis to linear scale

Category: Custom IC Design

By TB202408221839

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started over 1 year ago

0 replies • 485 views
Discussion

Merge buses when creating a symbol from SpectreText netlist

Category: Custom IC Design

By ArthurP

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started over 1 year ago

0 replies • 2709 views
Discussion

Can move component only up/down or left/right in Cadence Virtuoso

Category: Custom IC Design

By NN202501183253

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updated over 1 year ago by RobMan

1 replies • 1197 views
Discussion

analogLib/bsource component with complex coefficient

Category: Custom IC Design

By TommasoF

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updated over 1 year ago by TommasoF

3 replies • 1168 views
Discussion

Is it possible to access design variable as parameter of systemverilog bloc

Category: Custom IC Design

By Mathieu Chene

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started over 1 year ago

0 replies • 2658 views
Discussion

Issue OSSPDA with xcellium AMS sim

Category: Custom IC Design

By Binhngo1210

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started over 1 year ago

0 replies • 2623 views
Discussion

Descend menu - Set default preferences

Category: Custom IC Design

By strotta

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updated over 1 year ago by henker

1 replies • 601 views
Discussion

Synchronicity vs maestro view

Category: Custom IC Design

By StephanWeber

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updated over 1 year ago by Andrew Beckett

1 replies • 3000 views
Discussion

Colorcoding for low cpk in Yield-View in Assembler

Category: Custom IC Design

By leok

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updated over 1 year ago by StephanWeber

1 replies • 3349 views
Discussion

ADE output for conditional string from input logic combination

Category: Custom IC Design

By StephanWeber

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started over 1 year ago

0 replies • 2591 views
Discussion

back annotating bussed terminal DC voltages with cdsterm in Symbol

Category: Custom IC Design

By ebecheto

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updated over 1 year ago by ebecheto

4 replies • 3412 views

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