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Custom IC Design

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  • Discussion

    how to run the simulaiton for 1 ns step interval ..?

    Category: Custom IC Design

    By Sunil Kumar K Sunil Kumar K

    •

    updated over 15 years ago by Sunil Kumar K

    5 replies • 14242 views
  • Discussion

    Text output on Cadence Composer

    Category: Custom IC Design

    By archive archive

    •

    updated over 15 years ago by Andrew Beckett

    4 replies • 13479 views
  • Discussion

    creating a matrix of instances in verilog-A

    Category: Custom IC Design

    By rickrevolta rickrevolta

    •

    updated over 15 years ago by Andrew Beckett

    2 replies • 16359 views
  • Discussion

    Pin names

    Category: Custom IC Design

    By StreamCX StreamCX

    •

    updated over 15 years ago by Andrew Beckett

    7 replies • 10306 views
  • Discussion

    LvsIgnore Properties

    Category: Custom IC Design

    By frogconsultant frogconsultant

    •

    updated over 15 years ago by frogconsultant

    12 replies • 30395 views
  • Discussion

    How to implement this equation in VerilogA

    Category: Custom IC Design

    By princemahmmod princemahmmod

    •

    updated over 15 years ago by Andrew Beckett

    4 replies • 15641 views
  • Discussion

    Cadence 6 waveform error vpwl vsrc

    Category: Custom IC Design

    By StreamCX StreamCX

    •

    updated over 15 years ago by StreamCX

    9 replies • 9027 views
  • Discussion

    Output SPEF-file from QRC contains only top level ports

    Category: Custom IC Design

    By Slawa Slawa

    •

    updated over 15 years ago by Quek

    1 replies • 6093 views
  • Discussion

    Off-Grid pins warning in abstract generation

    Category: Custom IC Design

    By affaq affaq

    •

    updated over 15 years ago by Alex Soyer

    3 replies • 13792 views
  • Discussion

    subciruit initiated top-level current probe

    Category: Custom IC Design

    By Kalimero Kalimero

    •

    updated over 15 years ago by Kalimero

    5 replies • 16267 views
  • Discussion

    cadence verilog ams environment setup question

    Category: Custom IC Design

    By Wing2 Wing2

    •

    updated over 15 years ago by EricCDN

    1 replies • 18157 views
  • Discussion

    How to short small resistor for lvs purpose

    Category: Custom IC Design

    By harleyMax harleyMax

    •

    updated over 15 years ago by Andrew Beckett

    7 replies • 19168 views
  • Discussion

    Manual editing of a p2lvsfile

    Category: Custom IC Design

    By Slawa Slawa

    •

    updated over 15 years ago by Slawa

    6 replies • 7467 views
  • Discussion

    How to change the Internal Cell names

    Category: Custom IC Design

    By sathisha sathisha

    •

    updated over 15 years ago by Quek

    1 replies • 14454 views
  • Discussion

    ASSURA41-614: ERROR rcAddRegionTasks

    Category: Custom IC Design

    By tkhan tkhan

    •

    updated over 15 years ago by Andrew Beckett

    3 replies • 13327 views
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