Custom IC Design

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Discussion

ADE ViVA Plotting Template: Where is it stored and how to edit?

Category: Custom IC Design

By StephanWeber

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updated 2 months ago by StephanWeber

2 replies • 1079 views
Discussion

How to load viaGetViaOptions Function inside PCELL

Category: Custom IC Design

By Esteban Saavedra

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updated 3 months ago by Andrew Beckett

4 replies • 1152 views
Discussion

Any analogue or mixed signal Cadence FinFet layouts to share?

Category: Custom IC Design

By hesaliveJim

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started 3 months ago

0 replies • 772 views
Discussion

verilog Syntax errors not highlighted in text editor

Category: Custom IC Design

By JavierC

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updated 3 months ago by JavierC

6 replies • 1755 views
Discussion

Loading *WARNING* Connection to MACHINE failed. Connection refused

Category: Custom IC Design

By hesaliveJim

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updated 3 months ago by hesaliveJim

4 replies • 1133 views
Discussion

Any major difference between Cadence Advanced Node GPDK v1.0 and v1.1 release?

Category: Custom IC Design

By hesaliveJim

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updated 3 months ago by hesaliveJim

1 replies • 933 views
Discussion

best way to integrate different calibre extraction corners to virtuoso ADE

Category: Custom IC Design

By micipici

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updated 3 months ago by Andrew Beckett

1 replies • 925 views
Discussion

Distributed simulations

Category: Custom IC Design

By OPump

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updated 3 months ago by OPump

1 replies • 893 views
Discussion

Automatic routing --> All nets in Layout GXL of Cadence Virtuoso

Category: Custom IC Design

By hoangtn3702

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started 3 months ago

0 replies • 296 views
Discussion

How to plot a histogram of a relative error in a Monte Carlo analysis?

Category: Custom IC Design

By DomiHammerfall

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updated 3 months ago by DomiHammerfall

3 replies • 1192 views
Discussion

Unable to run Monte-Carlo simulation on ADE-XL

Category: Custom IC Design

By rtyuy

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updated 3 months ago by rtyuy

32 replies • 4115 views
Discussion

Error doing in Local Optimization in ADE Assembler

Category: Custom IC Design

By Bakr Abdelgaliel

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updated 3 months ago by Bakr Abdelgaliel

2 replies • 993 views
Discussion

spectre assert

Category: Custom IC Design

By Joe Mellon

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updated 3 months ago by Joe Mellon

2 replies • 1125 views
Discussion

Follow Up Discussion on Maestro can't save current with "WARNING (ADE-1063): The output with same signal '***' is already defined."

Category: Custom IC Design

By Kelsey Reed

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updated 3 months ago by Kelsey Reed

1 replies • 347 views
Discussion

How do I set default layout view for EM/IR data layout analysis Lib/Cell/View

Category: Custom IC Design

By BillH314

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started 3 months ago

0 replies • 216 views

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