Custom IC Design

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Discussion

Generating Liberty (.lib) File From Verilog-A Table Model

Category: Custom IC Design

By NKFET
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updated over 4 years ago by Guangjun Cao

3 replies • 12821 views
Discussion

How to add stop layers to annotation browser?

Category: Custom IC Design

By 94d33m
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started over 4 years ago

0 replies • 9022 views
Discussion

How to get phase noise from noise summary at paticular frequency?

Category: Custom IC Design

By Clara Dong
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updated over 4 years ago by FormerMember

2 replies • 10469 views
Discussion

Plotting a function on Cadence calculator that requires the temperature read from x-axsis

Category: Custom IC Design

By Senan
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updated over 4 years ago by FormerMember

3 replies • 12217 views
Discussion

How to make auto via feature in cadence avoid slot layers since it causes DRC violations?

Category: Custom IC Design

By 94d33m
•
updated over 4 years ago by Alex Soyer

1 replies • 9920 views
Discussion

How to formulate the "best fit line" in Vertuoso calculator

Category: Custom IC Design

By Senan
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updated over 4 years ago by Senan

2 replies • 2267 views
Discussion

cross function deficiency

Category: Custom IC Design

By CADcasualty
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updated over 4 years ago by CADcasualty

2 replies • 10340 views
Discussion

Format for montecarlo sweep in a *.scs file included with ADE Assembler

Category: Custom IC Design

By greywanderer
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updated over 4 years ago by greywanderer

2 replies • 9681 views
Discussion

SNR for Sigma Delta Modulator: Questions on Filter and DC Input

Category: Custom IC Design

By yizh
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started over 4 years ago

0 replies • 10476 views
Discussion

Could anyone explain this sampled noise simulation result

Category: Custom IC Design

By SpiceMonkey
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updated over 4 years ago by SpiceMonkey

9 replies • 17319 views
Discussion

Copy of group with MPP results in flattened MPP

Category: Custom IC Design

By LukiLeu
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started over 4 years ago

0 replies • 9154 views
Discussion

Can tests in Assembler use different config views?

Category: Custom IC Design

By Lawrence Guan
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updated over 4 years ago by Lawrence Guan

4 replies • 11064 views
Discussion

pnoise timedomain

Category: Custom IC Design

By Svilen64
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updated over 4 years ago by Svilen64

13 replies • 17918 views
Discussion

Disable "copy to cellview" option in ADE Variables

Category: Custom IC Design

By dnovikov
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updated over 4 years ago by Roly

7 replies • 3187 views
Discussion

How to see parents cell of a layout ?

Category: Custom IC Design

By 94d33m
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updated over 4 years ago by Andrew Beckett

1 replies • 9797 views

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