Custom IC Design

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Discussion

How can I import the model card to the Cadence?

Category: Custom IC Design

By yysunj
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updated over 4 years ago by yysunj

8 replies • 15004 views
Discussion

Need help with Cadence Virtuoso pop-ups display

Category: Custom IC Design

By Phong Phan
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updated over 4 years ago by Phong Phan

2 replies • 11875 views
Discussion

Is there a way to name matrixial instances or nets?

Category: Custom IC Design

By Johanny Saenz
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updated over 4 years ago by Andrew Beckett

1 replies • 10444 views
Discussion

Need to get routing layers info from tech db

Category: Custom IC Design

By Utkarsh03
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updated over 4 years ago by Utkarsh03

4 replies • 12176 views
Discussion

Monte carlo simulation error (no process variations were specified in the statistics block)

Category: Custom IC Design

By Afshin Amoo
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updated over 4 years ago by Afshin Amoo

2 replies • 14856 views
Discussion

oppoint using verilog a

Category: Custom IC Design

By Yea Chul
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updated over 4 years ago by Andrew Beckett

2 replies • 11870 views
Discussion

plotting loop gain in ADE Assembler

Category: Custom IC Design

By robert 21
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updated over 4 years ago by Andrew Beckett

4 replies • 13892 views
Discussion

implement noise behavior of transistor in spice code in spectre

Category: Custom IC Design

By Bo Yu
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updated over 4 years ago by Andrew Beckett

3 replies • 12956 views
Discussion

CCCS - controlling element not available

Category: Custom IC Design

By shlomo34
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updated over 4 years ago by shlomo34

4 replies • 3752 views
Discussion

Built-in aging model in TSMC PDK

Category: Custom IC Design

By FormerMember
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updated over 4 years ago by Andrew Beckett

3 replies • 4747 views
Discussion

ADE XL Monte Carlo analysis: statistical results are not available

Category: Custom IC Design

By Mike Tian
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updated over 4 years ago by KhanAmir

25 replies • 30713 views
Discussion

Reading IC5033 schematic in IC6.1.6 ?

Category: Custom IC Design

By Anon481
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updated over 4 years ago by Andrew Beckett

4 replies • 11536 views
Discussion

Dac verilog ams output FFT plot issue

Category: Custom IC Design

By sidm
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updated over 4 years ago by sidm

9 replies • 13483 views
Discussion

Instancing schematics in veriloga (or any other analog HDL)

Category: Custom IC Design

By BillH314
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started over 4 years ago

0 replies • 10490 views
Discussion

issue with extracted s parameter from EMX intergrand

Category: Custom IC Design

By tawsaras
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updated over 4 years ago by Andrew Beckett

1 replies • 11469 views

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