Custom IC Design

Latest Posts

Discussion

How can I replace a node name with another node name of all schematics in a Library?

Category: Custom IC Design

By ichiro
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started over 2 years ago

0 replies • 6380 views
Discussion

Adexl - dynamically stop transient run on event trigger

Category: Custom IC Design

By firebolt
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updated over 2 years ago by firebolt

11 replies • 4144 views
Discussion

portorder not being ignored?

Category: Custom IC Design

By kenc184
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updated over 2 years ago by kenc184

8 replies • 10016 views
Discussion

Is it possible to download the slides from online training?

Category: Custom IC Design

By delgsy
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updated over 2 years ago by Andrew Beckett

1 replies • 6321 views
Discussion

What does the cut pattern "farm" mean?

Category: Custom IC Design

By RVERP
•
updated over 2 years ago by RVERP

2 replies • 1015 views
Discussion

RLC parasitic extraction type for post-layout simulation

Category: Custom IC Design

By Senan
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updated over 2 years ago by Senan

5 replies • 9280 views
Discussion

Digital signal overshoot and undershoot detection in Cadence

Category: Custom IC Design

By Senan
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updated over 2 years ago by ShawnLogan

3 replies • 8089 views
Discussion

How to acces leaf-instance of subsckt for use as probe?

Category: Custom IC Design

By jehh
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started over 2 years ago

0 replies • 6325 views
Discussion

Spectre parallel jobs reduce near finish

Category: Custom IC Design

By Pirate King
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updated over 2 years ago by Cadenceuser101

6 replies • 9041 views
Discussion

Simulating a circuit in an array

Category: Custom IC Design

By delgsy
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updated over 2 years ago by Andrew Beckett

3 replies • 6906 views
Discussion

Virtuoso SystemVerilog errors

Category: Custom IC Design

By HoWei
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updated over 2 years ago by HoWei

14 replies • 14284 views
Discussion

Multiple alignment spacing parameters

Category: Custom IC Design

By Kevin Buck
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updated over 2 years ago by Kevin Buck

2 replies • 7019 views
Discussion

STB Analysis: Invalid instance name

Category: Custom IC Design

By fyoh
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updated over 2 years ago by fyoh

6 replies • 9333 views
Discussion

ADE Results "Detailed - Transposed" and CSV export: Missing spec and testname

Category: Custom IC Design

By StephanWeber
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updated over 2 years ago by StephanWeber

3 replies • 1551 views
Discussion

Magnitude value in AC simulation with Cadence Virtuoso

Category: Custom IC Design

By Senan
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updated over 2 years ago by ShawnLogan

11 replies • 18744 views

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