Custom IC Design

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Discussion

Guidelines for the Custom IC Design Forum

Category: Custom IC Design

By Andrew Beckett

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started over 14 years ago

0 replies • 30474 views
Discussion

PVS LVS with added external netlist

Category: Custom IC Design

By GBlasco

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updated 11 minutes ago by pchris

1 replies • 33 views
Discussion

Save multiple values versus frequency using spectremdl for spectre version 2016

Category: Custom IC Design

By GM202510215619

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updated 2 hours ago by GM202510215619

2 replies • 118 views
Discussion

Issue: SKILL Script Creates Schematic and Symbol But Ports Are Missing

Category: Custom IC Design

By Mooh

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updated 10 hours ago by Mooh

2 replies • 106 views
Discussion

Parasitic capacitance

Category: Custom IC Design

By SamanMKD

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updated 2 days ago by Andrew Beckett

3 replies • 157 views
Discussion

Request for Support with CDF Update Issue after importing .spi file in virtuoso

Category: Custom IC Design

By yogeshjaiswalCAD

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updated 6 days ago by yogeshjaiswalCAD

6 replies • 707 views
Discussion

Ocean XL: running the same script twice makes the CIW stuck

Category: Custom IC Design

By MC20250412421

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updated 6 days ago by MC20250412421

4 replies • 340 views
Discussion

Layout scaling and inconsistent shape dimensions issue.

Category: Custom IC Design

By JS20250120924

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updated 6 days ago by JS20250120924

4 replies • 342 views
Discussion

Simulating Encrypted PSpice Model from TI (CSD95373AQ5M)

Category: Custom IC Design

By WW202601034742

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updated 7 days ago by WW202601034742

3 replies • 313 views
Discussion

Short-resistor removal for LVS cleaning (Cadence Virtuoso + Pegasus)

Category: Custom IC Design

By yogeshjaiswalCAD

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started 11 days ago

0 replies • 217 views
Discussion

Virtuoso (IC25.1) startup very slow (~5mins) after Linux Update

Category: Custom IC Design

By mahodk

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updated 13 days ago by Andrew Beckett

1 replies • 339 views
Discussion

PVS window closes whenever trying to browse for a file

Category: Custom IC Design

By matangk2

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updated 14 days ago by Andrew Beckett

3 replies • 400 views
Discussion

Calibre PEX run error

Category: Custom IC Design

By SamanMKD

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updated 17 days ago by Andrew Beckett

1 replies • 322 views
Discussion

clock buffer output RJ and edge phase noise result "diverges"

Category: Custom IC Design

By Yuto Lau

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started 20 days ago

0 replies • 127 views
Discussion

Spectre noise analysis output size

Category: Custom IC Design

By SK202511261716

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updated 26 days ago by SK202511261716

2 replies • 558 views

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