Custom IC Design

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Discussion

Characterizing Transmission gate based cells for liberty file

Category: Custom IC Design

By NKFET
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updated over 3 years ago by Guangjun Cao

1 replies • 8709 views
Discussion

Cadence Viva Plots - customizing default legend display

Category: Custom IC Design

By firebolt
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updated over 3 years ago by firebolt

2 replies • 2480 views
Discussion

Can I prevent switching from Assembler to Explorer with single click?

Category: Custom IC Design

By StephanWeber
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updated over 3 years ago by FormerMember

1 replies • 7406 views
Discussion

converting transistors in a schematic from analogLib to technology library

Category: Custom IC Design

By Rezara
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updated over 3 years ago by FormerMember

3 replies • 8577 views
Discussion

Digital Vector File/How to Change the Voltage Level 3 Times

Category: Custom IC Design

By Omar Ghazal
•
started over 3 years ago

0 replies • 826 views
Discussion

How to run multiple analysis (ac, stb) in one test and make it work in Monte-Carlo simulation

Category: Custom IC Design

By sjwprcker
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started over 3 years ago

0 replies • 7895 views
Discussion

trapezoidal ringing with spectreX

Category: Custom IC Design

By sjwprcker
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updated over 3 years ago by sjwprcker

6 replies • 14888 views
Discussion

Cadence Vrituoso

Category: Custom IC Design

By younghyun
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updated over 3 years ago by pengchaoqun

6 replies • 10344 views
Discussion

Dc operating point info with spectre -X LX

Category: Custom IC Design

By sv srini
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started over 3 years ago

0 replies • 1706 views
Discussion

how to include the verilogA content in the netlist

Category: Custom IC Design

By sjwprcker
•
updated over 3 years ago by sjwprcker

7 replies • 11573 views
Discussion

Voltage jump in transient noise simulation when reading data from file

Category: Custom IC Design

By thegon
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updated over 3 years ago by FormerMember

3 replies • 9618 views
Discussion

Virtuoso Constraints SKILL code: correct my cstFindFirstConstraint syntax

Category: Custom IC Design

By dfink
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updated over 3 years ago by dfink

3 replies • 8316 views
Discussion

synthesizing Verilog code in Cadence Virtuoso

Category: Custom IC Design

By Senan
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updated over 3 years ago by Senan

2 replies • 10015 views
Discussion

Cellview generation from VHDL code in cadence 618

Category: Custom IC Design

By rovin
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updated over 3 years ago by rovin

5 replies • 10323 views
Discussion

.csv output in spectre

Category: Custom IC Design

By Yea Chul
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updated over 3 years ago by HTTb

11 replies • 11775 views

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