Custom IC Design

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Cadence Virtuoso Schematic: Input pin goes to 2 different nets

Category: Custom IC Design

By Piash

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updated over 3 years ago by Piash

2 replies • 10101 views
Discussion

skill command for remove of a netTrace

Category: Custom IC Design

By SpiceMonkey

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updated over 3 years ago by SpiceMonkey

1 replies • 8671 views
Discussion

Cadence Maestro - customizing results menu

Category: Custom IC Design

By firebolt

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updated over 3 years ago by firebolt

4 replies • 1991 views
Discussion

Cadence Schematic - hotkey for hiding terminal & instance labels

Category: Custom IC Design

By firebolt

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updated over 3 years ago by firebolt

2 replies • 2721 views
Discussion

Different Monte Carlo Setups in the same run/run plan (Maestro)

Category: Custom IC Design

By jackrc11

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updated over 3 years ago by Andrew Beckett

3 replies • 3928 views
Discussion

psfascii format

Category: Custom IC Design

By shaarawy2023

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updated over 3 years ago by Andrew Beckett

1 replies • 8607 views
Discussion

Layout integration

Category: Custom IC Design

By Arashka

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updated over 3 years ago by iq79

1 replies • 8184 views
Discussion

tsmc65nm DFM_options

Category: Custom IC Design

By zaki177

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updated over 3 years ago by iq79

2 replies • 8922 views
Discussion

pss+pstb simulation of boost converter when it is unstable

Category: Custom IC Design

By midaslab

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updated over 3 years ago by Andrew Beckett

3 replies • 2457 views
Discussion

spectre netlist

Category: Custom IC Design

By shaarawy2023

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updated over 3 years ago by Andrew Beckett

1 replies • 8589 views
Discussion

How to split device fingers in Virtuoso MODGEN

Category: Custom IC Design

By Nader Fathy

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updated over 3 years ago by Nader Fathy

1 replies • 9695 views
Discussion

How to read in a text file separated by delays in Verilog A. They delays are relative and to be read from the text file?

Category: Custom IC Design

By Nisharg shah

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started over 3 years ago

0 replies • 8061 views
Discussion

Simple example/template for a (matrix based, if possible) schematic pcell

Category: Custom IC Design

By SteveVrk

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updated over 3 years ago by SteveVrk

3 replies • 2480 views
Discussion

Accessing analog voltages in hierarchy from Verilog AMS

Category: Custom IC Design

By amacSS

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updated over 3 years ago by amacSS

4 replies • 10586 views
Discussion

use of calcVal() to access expressions from other tests

Category: Custom IC Design

By AncisMichele

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updated over 3 years ago by AncisMichele

4 replies • 19625 views

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