Custom IC Design

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Discussion

visibility toggle feature for instances in layout

Category: Custom IC Design

By delgsy

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updated over 3 years ago by delgsy

4 replies • 9838 views
Discussion

Assura isn't created 'run lvs' setting window

Category: Custom IC Design

By ehdwns48

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updated over 3 years ago by ehdwns48

3 replies • 1574 views
Discussion

Recent Files

Category: Custom IC Design

By RicardoGV1

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updated over 3 years ago by Andrew Beckett

3 replies • 8480 views
Discussion

Assembler: Measurement across sweep vs leaf values

Category: Custom IC Design

By StephanWeber

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updated over 3 years ago by MohNaj

2 replies • 9568 views
Discussion

Is it possible to hide instances?

Category: Custom IC Design

By Purbayan

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updated over 3 years ago by Andrew Beckett

3 replies • 9190 views
Discussion

Filter in ADE output results table for "eval error" and further filtering

Category: Custom IC Design

By StephanWeber

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started over 3 years ago

0 replies • 980 views
Discussion

VerilogA $abstime limitation to 2pi

Category: Custom IC Design

By Ajmal Hussian

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updated over 3 years ago by Andrew Beckett

6 replies • 10647 views
Discussion

While implementing SENT Rx Tx interface, the operating voltage is 5V in most of the paper for 0.18u technology, I am using 0.03u technology, kindly suggest the suitable voltage for this? cause if I am using high voltage MOS still not working?

Category: Custom IC Design

By CadenSr

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updated over 3 years ago by FormerMember

1 replies • 827 views
Discussion

How to add variable in Model file and Control the variable from ADE

Category: Custom IC Design

By AmarDas

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updated over 3 years ago by AmarDas

2 replies • 8293 views
Discussion

Does anyone know SUB layer used by Global Foundries 7sw

Category: Custom IC Design

By bford33

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started over 3 years ago

0 replies • 7635 views
Discussion

How to disable or automatically approve ADE assembler message 5067

Category: Custom IC Design

By alexstepanov75

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updated over 3 years ago by Andrew Beckett

1 replies • 8065 views
Discussion

Convergence Problem in Symica

Category: Custom IC Design

By SOU1995

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updated over 3 years ago by Andrew Beckett

1 replies • 8135 views
Discussion

Transfering a vector output of one test to another test in Assembler

Category: Custom IC Design

By baltacican

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updated over 3 years ago by Andrew Beckett

3 replies • 11046 views
Discussion

Does ADE license is necessary for export hspice netlist in virtuoso?

Category: Custom IC Design

By lightyear

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updated over 3 years ago by Andrew Beckett

1 replies • 9401 views
Discussion

How to find quickly the instances with largest current?

Category: Custom IC Design

By StephanWeber

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started over 3 years ago

0 replies • 7938 views

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