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Custom IC Design

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  • Discussion

    recovered transient simulation shows different waveform

    Category: Custom IC Design

    By an wx

    •

    started 10 months ago

    0 replies • 1606 views
  • Discussion

    Pnoise analysis with windowed sampling

    Category: Custom IC Design

    By ULPAnalog

    •

    started 10 months ago

    0 replies • 1587 views
  • Discussion

    fft function in the calculator is missing

    Category: Custom IC Design

    By kolep

    •

    updated 10 months ago by Andrew Beckett

    1 replies • 1771 views
  • Discussion

    Unable to update the number of MC point on the Run Plan

    Category: Custom IC Design

    By kolep

    •

    updated 10 months ago by Andrew Beckett

    1 replies • 1582 views
  • Discussion

    Virtuoso AMS NOUNIT error with Xcelium - Not caching libraries

    Category: Custom IC Design

    By AS202502163432

    •

    updated 10 months ago by AS202502163432

    8 replies • 4259 views
  • Discussion

    Recovering "actionable" netlist from GDS II

    Category: Custom IC Design

    By GS202507021424

    •

    updated 10 months ago by GS202507021424

    6 replies • 2680 views
  • Discussion

    How to reference multiple PWL waveforms from a single file in Spectre (vsource type=pwl)

    Category: Custom IC Design

    By baltaci

    •

    updated 10 months ago by Andrew Beckett

    1 replies • 2930 views
  • Discussion

    Copy schematic/symbol views hierarchically

    Category: Custom IC Design

    By ycau

    •

    updated 10 months ago by Andrew Beckett

    2 replies • 984 views
  • Discussion

    Transfer design variable from schematic / layout to av_extracted view

    Category: Custom IC Design

    By FM202408077836

    •

    updated 10 months ago by Andrew Beckett

    2 replies • 2281 views
  • Discussion

    Explanation of stb analysis results YG, YL, ZG, and ZL

    Category: Custom IC Design

    By Frank Wiedmann

    •

    started 10 months ago

    0 replies • 1848 views
  • Discussion

    Question on integrated noise in PNOISE (sampled) Noise summary

    Category: Custom IC Design

    By Yuto Lau

    •

    updated 10 months ago by Yuto Lau

    4 replies • 3072 views
  • Discussion

    Automating Layout Cell Updates Using SKILL with Cell List from File

    Category: Custom IC Design

    By AR202509246930

    •

    updated 10 months ago by Andrew Beckett

    1 replies • 2040 views
  • Discussion

    about cadence virtuoso guidance manual problem

    Category: Custom IC Design

    By JJ202503031042

    •

    updated 10 months ago by JJ202503031042

    3 replies • 2944 views
  • Discussion

    Creating Assura DRC rule to check that sep of 2 layers is exactly 2 different values

    Category: Custom IC Design

    By Miguel V

    •

    started 10 months ago

    0 replies • 1659 views
  • Discussion

    LVS Warning: “Unattached port label” for PLUS/MINUS on layer ind11_text — can’t locate device

    Category: Custom IC Design

    By RK202509013321

    •

    updated 10 months ago by RobMan

    3 replies • 2408 views
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