Custom IC Design

Latest Posts

Discussion

Virtuoso AMS NOUNIT error with Xcelium - Not caching libraries

Category: Custom IC Design

By AS202502163432
•
updated over 1 year ago by AS202502163432

8 replies • 4623 views
Discussion

Recovering "actionable" netlist from GDS II

Category: Custom IC Design

By GS202507021424
•
updated over 1 year ago by GS202507021424

6 replies • 3064 views
Discussion

How to reference multiple PWL waveforms from a single file in Spectre (vsource type=pwl)

Category: Custom IC Design

By baltaci
•
updated over 1 year ago by Andrew Beckett

1 replies • 3300 views
Discussion

Copy schematic/symbol views hierarchically

Category: Custom IC Design

By ycau
•
updated over 1 year ago by Andrew Beckett

2 replies • 1054 views
Discussion

Transfer design variable from schematic / layout to av_extracted view

Category: Custom IC Design

By FM202408077836
•
updated over 1 year ago by Andrew Beckett

2 replies • 2399 views
Discussion

Explanation of stb analysis results YG, YL, ZG, and ZL

Category: Custom IC Design

By Frank Wiedmann
•
started over 1 year ago

0 replies • 1938 views
Discussion

Question on integrated noise in PNOISE (sampled) Noise summary

Category: Custom IC Design

By Yuto Lau
•
updated over 1 year ago by Yuto Lau

4 replies • 3258 views
Discussion

Automating Layout Cell Updates Using SKILL with Cell List from File

Category: Custom IC Design

By AR202509246930
•
updated over 1 year ago by Andrew Beckett

1 replies • 2127 views
Discussion

about cadence virtuoso guidance manual problem

Category: Custom IC Design

By JJ202503031042
•
updated over 1 year ago by JJ202503031042

3 replies • 3066 views
Discussion

Creating Assura DRC rule to check that sep of 2 layers is exactly 2 different values

Category: Custom IC Design

By Miguel V
•
started over 1 year ago

0 replies • 1692 views
Discussion

LVS Warning: “Unattached port label” for PLUS/MINUS on layer ind11_text — can’t locate device

Category: Custom IC Design

By RK202509013321
•
updated over 1 year ago by RobMan

3 replies • 2682 views
Discussion

Dual Core Oscillator Open Loop

Category: Custom IC Design

By IS20250922772
•
started over 1 year ago

0 replies • 1469 views
Discussion

Assembler: possible to disable automatic evaluation of output expressions?

Category: Custom IC Design

By dontpanic
•
updated over 1 year ago by Andrew Beckett

1 replies • 1934 views
Discussion

Assembler: possible to force inclusion of model file(s) at the very beginning of netlist?

Category: Custom IC Design

By dontpanic
•
updated over 1 year ago by Andrew Beckett

3 replies • 1696 views
Discussion

Interactive mode for Spectre using Python/TCL

Category: Custom IC Design

By CB202409064221
•
updated over 1 year ago by Andrew Beckett

1 replies • 883 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.