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Custom IC Design

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  • Discussion

    Does Cadence provide a standard Python API for tool automation?

    Category: Custom IC Design

    By WM20250906725

    •

    updated 11 months ago by Andrew Beckett

    5 replies • 7146 views
  • Discussion

    Issue with the ADE Explorer/Assembler simulator

    Category: Custom IC Design

    By GL202502244954

    •

    started 11 months ago

    0 replies • 742 views
  • Discussion

    Date/time (or $system) in verilogA

    Category: Custom IC Design

    By leok

    •

    updated 11 months ago by leok

    2 replies • 1029 views
  • Discussion

    quantus parasitic extraction vs. SKY130 PDK

    Category: Custom IC Design

    By GS202507021424

    •

    updated 11 months ago by Andrew Beckett

    2 replies • 4623 views
  • Discussion

    Quantus Error – Sky130 qrcTechFile not recognized as valid technology file

    Category: Custom IC Design

    By RK202509013321

    •

    updated 11 months ago by Andrew Beckett

    1 replies • 3643 views
  • Discussion

    Stop Condition of Liberate trio in characterizing a DFF

    Category: Custom IC Design

    By TN202507027633

    •

    updated 11 months ago by Guangjun Cao

    1 replies • 2061 views
  • Discussion

    Virtuoso and Allegro Compatibility

    Category: Custom IC Design

    By forXTer

    •

    updated 11 months ago by Saloni Chhabra

    1 replies • 2032 views
  • Discussion

    IC25.1 Virtuoso crash but the simulation is still on going

    Category: Custom IC Design

    By sjwprcssw

    •

    started 11 months ago

    0 replies • 2046 views
  • Discussion

    How do you draw a parametrized layout of an inverter ?

    Category: Custom IC Design

    By MC20250412421

    •

    started 11 months ago

    0 replies • 1718 views
  • Discussion

    Is there any way to prevent my definition for model library from being overwritten by libInit.il of PDK while virtuoso starts up correctly?

    Category: Custom IC Design

    By zuiying

    •

    updated 11 months ago by zuiying

    2 replies • 2406 views
  • Discussion

    metal (or any dummy fill layer) skill code that can run at the block or chip level and automatically fill dummy metal in vacant spaces.

    Category: Custom IC Design

    By yogeshjaiswalCAD

    •

    updated 11 months ago by Andrew Beckett

    9 replies • 6036 views
  • Discussion

    How to define a parameter representing a path in globel model files?

    Category: Custom IC Design

    By zuiying

    •

    updated 11 months ago by Andrew Beckett

    1 replies • 2049 views
  • Discussion

    Cannot generate the EMIR report using 'emirreport'

    Category: Custom IC Design

    By aalbason

    •

    updated 11 months ago by Saloni Chhabra

    3 replies • 1637 views
  • Discussion

    EMIR Pin Current Results Discrepancy vs Transient Simulation Results

    Category: Custom IC Design

    By aalbason

    •

    started 11 months ago

    0 replies • 1747 views
  • Discussion

    Re: netlisting of verilogA block with choices for prompt in CDF

    Category: Custom IC Design

    By SL202411208815

    •

    started 11 months ago

    0 replies • 1629 views
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