Custom IC Design

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Discussion

PAC is giving 0V at the output

Category: Custom IC Design

By SA202512302438
•
updated over 1 year ago by Frank Wiedmann

2 replies • 2181 views
Discussion

Replace symbol pin names without changing the pin placement and symbol boundary

Category: Custom IC Design

By SimhanAnalog
•
updated over 1 year ago by SimhanAnalog

4 replies • 3259 views
Discussion

Which simulation tools are supported for Voltus-XFi within Virtuoso environment?

Category: Custom IC Design

By JY202510312553
•
started over 1 year ago

0 replies • 1610 views
Discussion

TSMC PDK Inductor Finder

Category: Custom IC Design

By nqthang
•
started over 1 year ago

0 replies • 2551 views
Discussion

Fundamental question on edge phase noise from sampled PNOISE

Category: Custom IC Design

By Yuto Lau
•
updated over 1 year ago by Yuto Lau

6 replies • 3816 views
Discussion

PWM block gain simulation using pss

Category: Custom IC Design

By TH202510293247
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started over 1 year ago

0 replies • 1389 views
Discussion

Cadence Virtuoso IC6.1.8 - Layout GXL Automatic Placement

Category: Custom IC Design

By hoangtn3702
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started over 1 year ago

0 replies • 1466 views
Discussion

wait a long time to have results updated

Category: Custom IC Design

By sjwprcssw
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started over 1 year ago

0 replies • 1618 views
Discussion

SOA analysis in cadence virtuoso

Category: Custom IC Design

By TUKA
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started over 1 year ago

0 replies • 2062 views
Discussion

Strategy for Accelerating Full-Chip AMS Simulation with Multi-Rate Clocks (1kHz / 100MHz)

Category: Custom IC Design

By HY202510149941
•
updated over 1 year ago by Alonso Schmidt

1 replies • 2199 views
Discussion

Buses in spectreText when creating symbol

Category: Custom IC Design

By MC20250412421
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updated over 1 year ago by MC20250412421

2 replies • 2601 views
Discussion

Does Cadence provide a standard Python API for tool automation?

Category: Custom IC Design

By WM20250906725
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updated over 1 year ago by Andrew Beckett

5 replies • 7581 views
Discussion

Issue with the ADE Explorer/Assembler simulator

Category: Custom IC Design

By GL202502244954
•
started over 1 year ago

0 replies • 802 views
Discussion

Date/time (or $system) in verilogA

Category: Custom IC Design

By leok
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updated over 1 year ago by leok

2 replies • 1084 views
Discussion

quantus parasitic extraction vs. SKY130 PDK

Category: Custom IC Design

By GS202507021424
•
updated over 1 year ago by Andrew Beckett

2 replies • 4953 views

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