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Custom IC Design

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  • Discussion

    Having Maestro report what DSPF view it used for each simulation

    Category: Custom IC Design

    By Mohsen2

    •

    started 10 months ago

    0 replies • 2064 views
  • Discussion

    ibis2subck for IBIS circuit doesn't extract analogmodel

    Category: Custom IC Design

    By JoseDuarte

    •

    started 10 months ago

    0 replies • 817 views
  • Discussion

    I am not able to select the layer while drawing a wire or a bus in Layout.

    Category: Custom IC Design

    By skillEater

    •

    updated 10 months ago by RobMan

    1 replies • 2617 views
  • Discussion

    How to mute WARNING This OS does not appear to be a Cadence supported Linux configuration

    Category: Custom IC Design

    By ebecheto

    •

    updated 10 months ago by Andrew Beckett

    1 replies • 3147 views
  • Discussion

    Modgen: How to add dummy FETs sharing diffusion without issues of marker layers?

    Category: Custom IC Design

    By sceekr

    •

    started 10 months ago

    0 replies • 3042 views
  • Discussion

    gsclib090 (gpdk090 standard cell library) download?

    Category: Custom IC Design

    By GS202507021424

    •

    updated 10 months ago by RobMan

    1 replies • 3751 views
  • Discussion

    Using VCSV File in Spectre Simulation

    Category: Custom IC Design

    By aalbason

    •

    updated 10 months ago by aalbason

    2 replies • 4191 views
  • Discussion

    Import HSpice Protected Netlist

    Category: Custom IC Design

    By JoseDuarte

    •

    updated 10 months ago by Andrew Beckett

    1 replies • 2890 views
  • Discussion

    Quantus PVS Parasitic Extraction ERROR (LBRCXM-992)

    Category: Custom IC Design

    By RV202509139743

    •

    started 10 months ago

    0 replies • 2539 views
  • Discussion

    Maestro ERROR for bus ">" when plot signals

    Category: Custom IC Design

    By LH202509171654

    •

    started 10 months ago

    0 replies • 755 views
  • Discussion

    Effect of Large Voltage (1 MV) on Accuracy When Using relref=sigglobal in Spectre APS/X

    Category: Custom IC Design

    By ycyang

    •

    started 10 months ago

    0 replies • 1040 views
  • Discussion

    Missing instance on LVS (IOs)

    Category: Custom IC Design

    By RV202509139743

    •

    started 10 months ago

    0 replies • 2563 views
  • Discussion

    Unmatched schematic pin label

    Category: Custom IC Design

    By RV202509139743

    •

    updated 10 months ago by RobMan

    1 replies • 3702 views
  • Discussion

    schViewToView symbol creation from systemverilog not working

    Category: Custom IC Design

    By SimhanAnalog

    •

    updated 10 months ago by rajeshcad

    9 replies • 5537 views
  • Discussion

    .proc file for TSMC65 for the EMX simulator

    Category: Custom IC Design

    By GL202502244954

    •

    updated 10 months ago by GL202502244954

    4 replies • 4367 views
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