Custom IC Design

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giolib045 "archaeology" (origin of giolib045.lib, giolib045.gds files)

Category: Custom IC Design

By GS202507021424
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started 10 months ago

0 replies • 495 views
Discussion

Schematic editor 2D array signal

Category: Custom IC Design

By kramnik
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updated 10 months ago by Andrew Beckett

1 replies • 2251 views
Discussion

automate creration of calibre view from extraction for multiple extracted corners

Category: Custom IC Design

By micipici
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updated 10 months ago by Andrew Beckett

1 replies • 2727 views
Discussion

Automatic routing using Cadence Virtuoso IC6.18.120

Category: Custom IC Design

By hoangtn3702
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started 10 months ago

0 replies • 2269 views
Discussion

How to greate guard ring for Cadence GPDK FinFet?

Category: Custom IC Design

By hesaliveJim
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updated 10 months ago by hesaliveJim

2 replies • 3010 views
Discussion

ADE ViVA Plotting Template: Where is it stored and how to edit?

Category: Custom IC Design

By StephanWeber
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updated 10 months ago by StephanWeber

2 replies • 2759 views
Discussion

How to load viaGetViaOptions Function inside PCELL

Category: Custom IC Design

By Esteban Saavedra
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updated 10 months ago by Andrew Beckett

4 replies • 2746 views
Discussion

Any analogue or mixed signal Cadence FinFet layouts to share?

Category: Custom IC Design

By hesaliveJim
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started 10 months ago

0 replies • 2075 views
Discussion

verilog Syntax errors not highlighted in text editor

Category: Custom IC Design

By JavierC
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updated 10 months ago by JavierC

6 replies • 4425 views
Discussion

Loading *WARNING* Connection to MACHINE failed. Connection refused

Category: Custom IC Design

By hesaliveJim
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updated 10 months ago by hesaliveJim

4 replies • 2706 views
Discussion

Any major difference between Cadence Advanced Node GPDK v1.0 and v1.1 release?

Category: Custom IC Design

By hesaliveJim
•
updated 10 months ago by hesaliveJim

1 replies • 2407 views
Discussion

best way to integrate different calibre extraction corners to virtuoso ADE

Category: Custom IC Design

By micipici
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updated 10 months ago by Andrew Beckett

1 replies • 2499 views
Discussion

Distributed simulations

Category: Custom IC Design

By OPump
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updated 10 months ago by OPump

1 replies • 2208 views
Discussion

Automatic routing --> All nets in Layout GXL of Cadence Virtuoso

Category: Custom IC Design

By hoangtn3702
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started 10 months ago

0 replies • 553 views
Discussion

How to plot a histogram of a relative error in a Monte Carlo analysis?

Category: Custom IC Design

By DomiHammerfall
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updated 10 months ago by DomiHammerfall

3 replies • 3141 views

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