Custom IC Design

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Discussion

Unable to run Monte-Carlo simulation on ADE-XL

Category: Custom IC Design

By rtyuy
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updated 10 months ago by rtyuy

32 replies • 9073 views
Discussion

Error doing in Local Optimization in ADE Assembler

Category: Custom IC Design

By Bakr Abdelgaliel
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updated 10 months ago by Bakr Abdelgaliel

2 replies • 2535 views
Discussion

spectre assert

Category: Custom IC Design

By Joe Mellon
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updated 10 months ago by Joe Mellon

2 replies • 2645 views
Discussion

Follow Up Discussion on Maestro can't save current with "WARNING (ADE-1063): The output with same signal '***' is already defined."

Category: Custom IC Design

By Kelsey Reed
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updated 10 months ago by Kelsey Reed

1 replies • 521 views
Discussion

How do I set default layout view for EM/IR data layout analysis Lib/Cell/View

Category: Custom IC Design

By BillH314
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started 10 months ago

0 replies • 351 views
Discussion

The drain and source is different direction in pex with different fingers of the same mos

Category: Custom IC Design

By dogman4
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updated 10 months ago by Andrew Beckett

1 replies • 2372 views
Discussion

The current direction is different after simulation with different fingers of the same mos

Category: Custom IC Design

By dogman4
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updated 10 months ago by dogman4

3 replies • 2824 views
Discussion

Generate steamOut.map for Innovus GDS export in Virtuoso?

Category: Custom IC Design

By Gurjot Singh
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updated 10 months ago by Andrew Beckett

1 replies • 2746 views
Discussion

information about (description of) gsclib045 components?

Category: Custom IC Design

By GS202507021424
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updated 10 months ago by GS202507021424

2 replies • 2772 views
Discussion

VIVA: Change color/disable highlighting around current (sub-)window

Category: Custom IC Design

By dontpanic
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updated 10 months ago by dontpanic

6 replies • 1379 views
Discussion

Problems with genvar and nested for loops in verilog-A after updating the Cadence tools

Category: Custom IC Design

By Esmee Tackx
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started 10 months ago

0 replies • 2614 views
Discussion

Latency to Connect License server

Category: Custom IC Design

By Tarique mohd
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updated 10 months ago by Saloni Chhabra

3 replies • 3162 views
Discussion

Parasitic Extraction Failure in Quantus - Assura

Category: Custom IC Design

By MK202507103018
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started 10 months ago

0 replies • 377 views
Discussion

Netlisting 'config' view with SPICE source file... CDF parameter m= on symbol is not printed in netlist instance call

Category: Custom IC Design

By JeffBeck
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updated 11 months ago by JeffBeck

2 replies • 1147 views
Discussion

pxf or pac sampled Explanation

Category: Custom IC Design

By Patrick Chang
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started 11 months ago

0 replies • 2301 views

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