Custom IC Design

Latest Posts

Discussion

Could not find netlist procedure:SpectreFNPairs instance

Category: Custom IC Design

By ranaya
•
updated over 1 year ago by Andrew Beckett

5 replies • 2518 views
Discussion

LUT implementation using VerilogA code In Cadence Virtuoso

Category: Custom IC Design

By ZulfiqarKiani
•
started over 1 year ago

0 replies • 2782 views
Discussion

Sorting variables by name alphanumerically in Virtuoso ADE Assembler / maestro

Category: Custom IC Design

By Dominique8765
•
updated over 1 year ago by Andrew Beckett

1 replies • 2193 views
Discussion

sweeping transistor number of fingers in a simulation

Category: Custom IC Design

By TommasoF
•
updated over 1 year ago by TommasoF

2 replies • 2807 views
Discussion

xrun: *F,SROOTE: Cannot find the Spectre installation

Category: Custom IC Design

By Leo 93
•
updated over 1 year ago by Andrew Beckett

3 replies • 1912 views
Discussion

use DC sweep variable to set another variable

Category: Custom IC Design

By Darrell L
•
updated over 1 year ago by Darrell L

2 replies • 2616 views
Discussion

automate cadence design to avoid time consuming steps for simulation using python subprocess module.

Category: Custom IC Design

By AP202507218251
•
started over 1 year ago

0 replies • 1979 views
Discussion

ERROR (NVN-13010): Cell rupolym is not defined while running Pegasus LVS

Category: Custom IC Design

By yogeshjaiswalCAD
•
updated over 1 year ago by Andrew Beckett

3 replies • 2921 views
Discussion

All pins on schematics unconnected to their attached wires when importing EDIF from Siemens,

Category: Custom IC Design

By DavidGogiber
•
updated over 1 year ago by Andrew Beckett

4 replies • 3988 views
Discussion

Cannot Copy Variable to Other Tests

Category: Custom IC Design

By MM202507017815
•
updated over 1 year ago by Andrew Beckett

1 replies • 2263 views
Discussion

Cadence PEX Directory Creation - Unable to Create the Directory for Netlist

Category: Custom IC Design

By ranaya
•
updated over 1 year ago by ranaya

2 replies • 1254 views
Discussion

Cadence Parasitic Extraction - Location / Directory Issue

Category: Custom IC Design

By ranaya
•
updated over 1 year ago by Andrew Beckett

1 replies • 942 views
Discussion

Automating Library Reference Change with Additional Parameters in New Library

Category: Custom IC Design

By AN202507174258
•
started over 1 year ago

0 replies • 2266 views
Discussion

For a new machine, which RHEL?

Category: Custom IC Design

By kenc184
•
updated over 1 year ago by kenc184

3 replies • 4732 views
Discussion

Parameterization of transistor model BSIM4 parameters

Category: Custom IC Design

By Sourav Chakraborty
•
started over 1 year ago

0 replies • 2137 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.