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Custom IC Design

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  • Discussion

    giolib045 "archaeology" (origin of giolib045.lib, giolib045.gds files)

    Category: Custom IC Design

    By GS202507021424

    •

    started 11 months ago

    0 replies • 543 views
  • Discussion

    Schematic editor 2D array signal

    Category: Custom IC Design

    By kramnik

    •

    updated 11 months ago by Andrew Beckett

    1 replies • 2341 views
  • Discussion

    automate creration of calibre view from extraction for multiple extracted corners

    Category: Custom IC Design

    By micipici

    •

    updated 11 months ago by Andrew Beckett

    1 replies • 2918 views
  • Discussion

    Automatic routing using Cadence Virtuoso IC6.18.120

    Category: Custom IC Design

    By hoangtn3702

    •

    started over 1 year ago

    0 replies • 2378 views
  • Discussion

    How to greate guard ring for Cadence GPDK FinFet?

    Category: Custom IC Design

    By hesaliveJim

    •

    updated over 1 year ago by hesaliveJim

    2 replies • 3238 views
  • Discussion

    ADE ViVA Plotting Template: Where is it stored and how to edit?

    Category: Custom IC Design

    By StephanWeber

    •

    updated over 1 year ago by StephanWeber

    2 replies • 2963 views
  • Discussion

    How to load viaGetViaOptions Function inside PCELL

    Category: Custom IC Design

    By Esteban Saavedra

    •

    updated over 1 year ago by Andrew Beckett

    4 replies • 2941 views
  • Discussion

    Any analogue or mixed signal Cadence FinFet layouts to share?

    Category: Custom IC Design

    By hesaliveJim

    •

    started over 1 year ago

    0 replies • 2130 views
  • Discussion

    verilog Syntax errors not highlighted in text editor

    Category: Custom IC Design

    By JavierC

    •

    updated over 1 year ago by JavierC

    6 replies • 4916 views
  • Discussion

    Loading *WARNING* Connection to MACHINE failed. Connection refused

    Category: Custom IC Design

    By hesaliveJim

    •

    updated over 1 year ago by hesaliveJim

    4 replies • 2867 views
  • Discussion

    Any major difference between Cadence Advanced Node GPDK v1.0 and v1.1 release?

    Category: Custom IC Design

    By hesaliveJim

    •

    updated over 1 year ago by hesaliveJim

    1 replies • 2527 views
  • Discussion

    best way to integrate different calibre extraction corners to virtuoso ADE

    Category: Custom IC Design

    By micipici

    •

    updated over 1 year ago by Andrew Beckett

    1 replies • 2694 views
  • Discussion

    Distributed simulations

    Category: Custom IC Design

    By OPump

    •

    updated over 1 year ago by OPump

    1 replies • 2294 views
  • Discussion

    Automatic routing --> All nets in Layout GXL of Cadence Virtuoso

    Category: Custom IC Design

    By hoangtn3702

    •

    started over 1 year ago

    0 replies • 624 views
  • Discussion

    How to plot a histogram of a relative error in a Monte Carlo analysis?

    Category: Custom IC Design

    By DomiHammerfall

    •

    updated over 1 year ago by DomiHammerfall

    3 replies • 3561 views
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