Custom IC Design

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Discussion

Can move component only up/down or left/right in Cadence Virtuoso

Category: Custom IC Design

By NN202501183253

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updated 9 months ago by RobMan

1 replies • 856 views
Discussion

analogLib/bsource component with complex coefficient

Category: Custom IC Design

By TommasoF

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updated 9 months ago by TommasoF

3 replies • 904 views
Discussion

Is it possible to access design variable as parameter of systemverilog bloc

Category: Custom IC Design

By Mathieu Chene

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started 9 months ago

0 replies • 1951 views
Discussion

Issue OSSPDA with xcellium AMS sim

Category: Custom IC Design

By Binhngo1210

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started 9 months ago

0 replies • 1940 views
Discussion

Descend menu - Set default preferences

Category: Custom IC Design

By strotta

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updated 9 months ago by henker

1 replies • 482 views
Discussion

Synchronicity vs maestro view

Category: Custom IC Design

By StephanWeber

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updated 9 months ago by Andrew Beckett

1 replies • 2188 views
Discussion

Colorcoding for low cpk in Yield-View in Assembler

Category: Custom IC Design

By leok

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updated 9 months ago by StephanWeber

1 replies • 2657 views
Discussion

ADE output for conditional string from input logic combination

Category: Custom IC Design

By StephanWeber

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started 9 months ago

0 replies • 1919 views
Discussion

back annotating bussed terminal DC voltages with cdsterm in Symbol

Category: Custom IC Design

By ebecheto

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updated 9 months ago by ebecheto

4 replies • 2547 views
Discussion

Unable to run PVS Quantus extraction in cds_ff_mpt (finfet 18nm)

Category: Custom IC Design

By nikhil2798gp

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updated 9 months ago by Ganesh

6 replies • 3070 views
Discussion

Characterizing cells with verilog-A models by liberate, but the model or instance can not be found

Category: Custom IC Design

By RL202501168650

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updated 9 months ago by Guangjun Cao

7 replies • 4131 views
Discussion

how to start virtuoso with multi-core(cpu)?

Category: Custom IC Design

By Yush

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updated 9 months ago by Andrew Beckett

1 replies • 644 views
Discussion

Transient Analysis Terminated without error message

Category: Custom IC Design

By JK20250114453

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updated 9 months ago by Andrew Beckett

1 replies • 2104 views
Discussion

Export assembler measurement to vcsv files

Category: Custom IC Design

By TH20240912844

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updated 9 months ago by TH20240912844

2 replies • 2338 views
Discussion

How to use the array index to parametrize the delay

Category: Custom IC Design

By Svilen64

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updated 9 months ago by Andrew Beckett

1 replies • 2053 views

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