Custom IC Design

Latest Posts

Discussion

ADE ViVA Plotting Template: Where is it stored and how to edit?

Category: Custom IC Design

By StephanWeber
•
updated over 1 year ago by StephanWeber

2 replies • 3123 views
Discussion

How to load viaGetViaOptions Function inside PCELL

Category: Custom IC Design

By Esteban Saavedra
•
updated over 1 year ago by Andrew Beckett

4 replies • 3086 views
Discussion

Any analogue or mixed signal Cadence FinFet layouts to share?

Category: Custom IC Design

By hesaliveJim
•
started over 1 year ago

0 replies • 2171 views
Discussion

verilog Syntax errors not highlighted in text editor

Category: Custom IC Design

By JavierC
•
updated over 1 year ago by JavierC

6 replies • 5292 views
Discussion

Loading *WARNING* Connection to MACHINE failed. Connection refused

Category: Custom IC Design

By hesaliveJim
•
updated over 1 year ago by hesaliveJim

4 replies • 2996 views
Discussion

Any major difference between Cadence Advanced Node GPDK v1.0 and v1.1 release?

Category: Custom IC Design

By hesaliveJim
•
updated over 1 year ago by hesaliveJim

1 replies • 2609 views
Discussion

best way to integrate different calibre extraction corners to virtuoso ADE

Category: Custom IC Design

By micipici
•
updated over 1 year ago by Andrew Beckett

1 replies • 2827 views
Discussion

Distributed simulations

Category: Custom IC Design

By OPump
•
updated over 1 year ago by OPump

1 replies • 2342 views
Discussion

Automatic routing --> All nets in Layout GXL of Cadence Virtuoso

Category: Custom IC Design

By hoangtn3702
•
started over 1 year ago

0 replies • 706 views
Discussion

How to plot a histogram of a relative error in a Monte Carlo analysis?

Category: Custom IC Design

By DomiHammerfall
•
updated over 1 year ago by DomiHammerfall

3 replies • 3891 views
Discussion

Unable to run Monte-Carlo simulation on ADE-XL

Category: Custom IC Design

By rtyuy
•
updated over 1 year ago by rtyuy

32 replies • 11208 views
Discussion

Error doing in Local Optimization in ADE Assembler

Category: Custom IC Design

By Bakr Abdelgaliel
•
updated over 1 year ago by Bakr Abdelgaliel

2 replies • 2872 views
Discussion

spectre assert

Category: Custom IC Design

By Joe Mellon
•
updated over 1 year ago by Joe Mellon

2 replies • 2969 views
Discussion

Follow Up Discussion on Maestro can't save current with "WARNING (ADE-1063): The output with same signal '***' is already defined."

Category: Custom IC Design

By Kelsey Reed
•
updated over 1 year ago by Kelsey Reed

1 replies • 611 views
Discussion

How do I set default layout view for EM/IR data layout analysis Lib/Cell/View

Category: Custom IC Design

By BillH314
•
started over 1 year ago

0 replies • 414 views

Custom IC Design

Latest Posts

ADE ViVA Plotting Template: Where is it stored and how to edit?

How to load viaGetViaOptions Function inside PCELL

Any analogue or mixed signal Cadence FinFet layouts to share?

verilog Syntax errors not highlighted in text editor

Loading WARNING Connection to MACHINE failed. Connection refused

Any major difference between Cadence Advanced Node GPDK v1.0 and v1.1 release?

best way to integrate different calibre extraction corners to virtuoso ADE

Distributed simulations

Automatic routing --> All nets in Layout GXL of Cadence Virtuoso

How to plot a histogram of a relative error in a Monte Carlo analysis?

Unable to run Monte-Carlo simulation on ADE-XL

Error doing in Local Optimization in ADE Assembler

spectre assert

Follow Up Discussion on Maestro can't save current with "WARNING (ADE-1063): The output with same signal '***' is already defined."

How do I set default layout view for EM/IR data layout analysis Lib/Cell/View

Community Guidelines