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Custom IC Design

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  • Discussion

    How to combine two procedure syntax and use by bindkey layer?

    Category: Custom IC Design

    By toyakoyosu toyakoyosu

    •

    updated over 4 years ago by Andrew Beckett

    3 replies • 10867 views
  • Discussion

    Controlling the displayed number of floating decimals in the DC operating point

    Category: Custom IC Design

    By Javier Beloso Javier Beloso

    •

    updated over 4 years ago by Javier Beloso

    2 replies • 13086 views
  • Discussion

    Setting for setting the analog stimuli

    Category: Custom IC Design

    By sidm sidm

    •

    updated over 4 years ago by sidm

    4 replies • 13944 views
  • Discussion

    How to move symbol origin for only SOME instances

    Category: Custom IC Design

    By Ahmed A Elsayed Ahmed A Elsayed

    •

    updated over 4 years ago by Ahmed A Elsayed

    3 replies • 11852 views
  • Discussion

    dynamic stop time in transient analysis

    Category: Custom IC Design

    By Hazem Al Indari Hazem Al Indari

    •

    updated over 4 years ago by Marc Heise

    5 replies • 14815 views
  • Discussion

    No such feature exists. error from lmutil lmdiag command

    Category: Custom IC Design

    By Layne Bunker Layne Bunker

    •

    updated over 4 years ago by Frank Wiedmann

    2 replies • 12086 views
  • Discussion

    DSPF cellview in Hierarchy Editor will be always netlisted with "subcircuit" model name

    Category: Custom IC Design

    By ZoltanT ZoltanT

    •

    updated over 4 years ago by ZoltanT

    7 replies • 4906 views
  • Discussion

    Stretching multiple layout wires at once

    Category: Custom IC Design

    By hesdeadJim hesdeadJim

    •

    updated over 4 years ago by Andrew Beckett

    4 replies • 13277 views
  • Discussion

    Defining supply voltage (and basic connect rules) for digital block for runams

    Category: Custom IC Design

    By jehh jehh

    •

    updated over 4 years ago by jehh

    2 replies • 12207 views
  • Discussion

    Stop an area of a schematic being netlisted.

    Category: Custom IC Design

    By FAwqati FAwqati

    •

    updated over 4 years ago by FAwqati

    4 replies • 11300 views
  • Discussion

    Does PNOISE sim of a sample & hold circuit include clock jitter effect?

    Category: Custom IC Design

    By peter6g peter6g

    •

    updated over 4 years ago by Andrew Beckett

    6 replies • 5339 views
  • Discussion

    How to exploit annotation browser connectivity for custom cells?

    Category: Custom IC Design

    By YJ Jo YJ Jo

    •

    updated over 4 years ago by Andrew Beckett

    5 replies • 11422 views
  • Discussion

    Variable net name in Virtuoso

    Category: Custom IC Design

    By VysakhK VysakhK

    •

    updated over 4 years ago by Andrew Beckett

    1 replies • 11354 views
  • Discussion

    Generating real random number in AMS

    Category: Custom IC Design

    By RFStuff RFStuff

    •

    updated over 4 years ago by RFStuff

    2 replies • 11961 views
  • Discussion

    DC operation point only print limited results

    Category: Custom IC Design

    By Biasing Biasing

    •

    updated over 4 years ago by Biasing

    2 replies • 11787 views
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