Custom IC Design

Latest Posts

Discussion

DEFT

Category: Custom IC Design

By samer1

$usertype
•
updated over 8 years ago by Andrew Beckett

3 replies • 13608 views
Discussion

Setting up a jitter simulation

Category: Custom IC Design

By itos

$usertype
•
updated over 8 years ago by Andrew Beckett

1 replies • 28658 views
Discussion

Performing Parasitic Extraction on a Layout which Contains an ADS Momentum Cell

Category: Custom IC Design

By canbaltaci

$usertype
•
updated over 8 years ago by Andrew Beckett

1 replies • 14939 views
Discussion

custom VCCS

Category: Custom IC Design

By Sali

$usertype
•
updated over 8 years ago by Andrew Beckett

4 replies • 16070 views
Discussion

Extracted simulation not working properly - netlist problem...?

Category: Custom IC Design

By cescoz

$usertype
•
updated over 8 years ago by Andrew Beckett

5 replies • 4880 views
Discussion

How to prevent automatically opening spectre.out in ViewFile-Window when running a simulation?

Category: Custom IC Design

By Magistus

$usertype
•
updated over 8 years ago by Magistus

2 replies • 14083 views
Discussion

viewing spectre simulation results right from the start

Category: Custom IC Design

By memphis

$usertype
•
updated over 8 years ago by memphis

3 replies • 15541 views
Discussion

Changing the I/O Type of a Pin in Layout View Using SKILL

Category: Custom IC Design

By canbaltaci

$usertype
•
updated over 8 years ago by canbaltaci

2 replies • 2561 views
Discussion

Problem in simulating SPICE model in spectre

Category: Custom IC Design

By farhan89

$usertype
•
updated over 8 years ago by Andrew Beckett

1 replies • 16388 views
Discussion

Cadence DRC Environment vars

Category: Custom IC Design

By samer1

$usertype
•
updated over 8 years ago by Andrew Beckett

1 replies • 14577 views
Discussion

Problem with simulating a PVS ERC spice netlist in spectre plus a skill for spice netlist reduction

Category: Custom IC Design

By RaghavasimhanT

$usertype
•
updated over 8 years ago by Andrew Beckett

2 replies • 14452 views
Discussion

ead_workshop - ade-xl error message (1921)

Category: Custom IC Design

By rafaelon

$usertype
•
updated over 8 years ago by Andrew Beckett

4 replies • 4964 views
Discussion

Creating digital buses in ADE XL: awvCreateBus

Category: Custom IC Design

By PNadeau

$usertype
•
updated over 8 years ago by prashantpd

3 replies • 19944 views
Discussion

Continuous Path/Routing with Varying Width

Category: Custom IC Design

By canbaltaci

$usertype
•
updated over 8 years ago by canbaltaci

2 replies • 1125 views
Discussion

Can i make the design rule check blind to a specific layer?

Category: Custom IC Design

By samer1

$usertype
•
updated over 8 years ago by samer1

6 replies • 14480 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.