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Custom IC Design

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  • Discussion

    Optimize and speed up automatic routing

    Category: Custom IC Design

    By RuihW RuihW

    •

    started over 1 year ago

    0 replies • 4057 views
  • Discussion

    Problem on connect all the bus lines together.

    Category: Custom IC Design

    By SMaxwell SMaxwell

    •

    started over 1 year ago

    0 replies • 4398 views
  • Discussion

    Tran simulation results can't be saved when using XPS MS and enabling post-layout optimization?

    Category: Custom IC Design

    By zuiying zuiying

    •

    updated over 1 year ago by Andrew Beckett

    1 replies • 1844 views
  • Discussion

    Can not change instance in schematic view

    Category: Custom IC Design

    By Omar Ghazal Omar Ghazal

    •

    updated over 1 year ago by Omar Ghazal

    2 replies • 4713 views
  • Discussion

    Fail to generate netlist as cell view specified to a SPICE file in Hierarchy Editor

    Category: Custom IC Design

    By Leo66 Leo66

    •

    updated over 1 year ago by Leo66

    4 replies • 6124 views
  • Discussion

    XF Analysis: How to save transfer function from only certain sources?

    Category: Custom IC Design

    By Matthew Love Matthew Love

    •

    updated over 1 year ago by Matthew Love

    2 replies • 4323 views
  • Discussion

    Virtuoso adexl relxpert aging simulation is disabled

    Category: Custom IC Design

    By Holz Holz

    •

    started over 1 year ago

    0 replies • 3926 views
  • Discussion

    Problem with using a genvar in if statement in Verilog-a

    Category: Custom IC Design

    By Esmee Tackx Esmee Tackx

    •

    started over 1 year ago

    0 replies • 4350 views
  • Discussion

    Ignore dummies in PVS using GPDK 45nm [solved]

    Category: Custom IC Design

    By hesaliveJim hesaliveJim

    •

    updated over 1 year ago by RobMan

    6 replies • 5909 views
  • Discussion

    Unable to open the waveform file `ecg/.csv'. Ensure that the specified file or directory exists.

    Category: Custom IC Design

    By AvaHeda AvaHeda

    •

    updated over 1 year ago by Andrew Beckett

    1 replies • 1275 views
  • Discussion

    Re-evaluating an "eval err" expression after simulation

    Category: Custom IC Design

    By RuihW RuihW

    •

    updated over 1 year ago by RuihW

    4 replies • 3952 views
  • Discussion

    Where are Custom Calculator Functions stored when loaded by fx button

    Category: Custom IC Design

    By Volker T Volker T

    •

    updated over 1 year ago by Volker T

    2 replies • 4585 views
  • Discussion

    Is there a Calculator function like firstVal to get the y-value

    Category: Custom IC Design

    By Volker T Volker T

    •

    updated over 1 year ago by Volker T

    3 replies • 5211 views
  • Discussion

    Encountered a fatal error while compiling the ahdlcmi module library

    Category: Custom IC Design

    By Sami048 Sami048

    •

    updated over 1 year ago by Andrew Beckett

    3 replies • 5131 views
  • Discussion

    mmsim_genplugin documentation for compiling C/C++ functions for VerilogA

    Category: Custom IC Design

    By ccsim ccsim

    •

    updated over 1 year ago by ccsim

    2 replies • 1057 views
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