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Digital Implementation

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  • Discussion

    How to select routing layer pitch?

    Category: Digital Implementation

    By Tongju

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    updated over 13 years ago by Kari

    1 replies • 13903 views
  • Discussion

    difficult encounter

    Category: Digital Implementation

    By Sardar

    $usertype

    •

    updated over 13 years ago by Kari

    2 replies • 13477 views
  • Discussion

    use of SPEF file

    Category: Digital Implementation

    By gops

    $usertype

    •

    updated over 13 years ago by Kari

    6 replies • 18805 views
  • Discussion

    Antenna violation

    Category: Digital Implementation

    By surajece01

    $usertype

    •

    updated over 13 years ago by Kari

    1 replies • 13564 views
  • Discussion

    Mix auto and manual P&R (in Cadence Encounter)

    Category: Digital Implementation

    By Shurik

    $usertype

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    updated over 13 years ago by Kari

    1 replies • 1009 views
  • Discussion

    Unused Reset Buffers

    Category: Digital Implementation

    By Johann Glaser

    $usertype

    •

    updated over 13 years ago by Kari

    1 replies • 13258 views
  • Discussion

    Assura BlackBox LVS issue + un-named Pins in imported layout in virtuoso

    Category: Digital Implementation

    By MOAAZ AHMED

    $usertype

    •

    updated over 13 years ago by Kari

    1 replies • 14291 views
  • Discussion

    Floorplan Guides not loaded

    Category: Digital Implementation

    By Johann Glaser

    $usertype

    •

    updated over 13 years ago by Kari

    1 replies • 13328 views
  • Discussion

    How we will Validate SDC??

    Category: Digital Implementation

    By Ashok Nellore

    $usertype

    •

    updated over 13 years ago by Kari

    3 replies • 15242 views
  • Discussion

    Do we remove scan chain before placement and reconnected after routing ?

    Category: Digital Implementation

    By Ashok Nellore

    $usertype

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    updated over 13 years ago by Kari

    1 replies • 14590 views
  • Discussion

    How to calculate Die size for core limited and Pad limited design?

    Category: Digital Implementation

    By Ashok Nellore

    $usertype

    •

    updated over 13 years ago by Kari

    2 replies • 17277 views
  • Discussion

    Assemble Design with netlist and def

    Category: Digital Implementation

    By Nishant

    $usertype

    •

    updated over 13 years ago by Kari

    1 replies • 13891 views
  • Discussion

    Fixing max transition violation

    Category: Digital Implementation

    By mwhite

    $usertype

    •

    updated over 13 years ago by Kari

    3 replies • 20421 views
  • Discussion

    setPlaceMode switches

    Category: Digital Implementation

    By DSubbu

    $usertype

    •

    started over 13 years ago

    0 replies • 13994 views
  • Discussion

    SOC Encounter power plan & Virtuoso Layout vdd! soft pin

    Category: Digital Implementation

    By Thodoros

    $usertype

    •

    started over 13 years ago

    0 replies • 595 views
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