Digital Implementation

Latest Posts

Discussion

Confusion related to fixing setup violation using ECO.....................:(

Category: Digital Implementation

By Hardeep
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started over 14 years ago

0 replies • 12856 views
Discussion

placeDesign uses trialRoute

Category: Digital Implementation

By Johann Glaser
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started over 14 years ago

0 replies • 12980 views
Discussion

"optDesign -preCTS" doesn't seem to be optimizing

Category: Digital Implementation

By Brannon
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updated over 14 years ago by Brannon

2 replies • 2215 views
Discussion

How can I specify the number of cores RTL compiler uses for processing?

Category: Digital Implementation

By mamsadegh
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updated over 14 years ago by grasshopper

1 replies • 13995 views
Discussion

ELC - illegal "complementary" in gate file

Category: Digital Implementation

By MzQuarter
•
started over 14 years ago

0 replies • 292 views
Discussion

Inserting diode in fixing antenna

Category: Digital Implementation

By MaK78
•
updated over 14 years ago by MaK78

5 replies • 15693 views
Discussion

*Fence* *SRC* *MME* Buffers in Clock Tree

Category: Digital Implementation

By Nataraja G
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updated over 14 years ago by Nataraja G

2 replies • 13220 views
Discussion

Multiple Pin Metal Layer

Category: Digital Implementation

By Kevin P Thomas
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updated over 14 years ago by Kari

1 replies • 13109 views
Discussion

route selected nets using nanoroute

Category: Digital Implementation

By fallfly
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updated over 14 years ago by Kari

1 replies • 13591 views
Discussion

Changing the floorplan origin

Category: Digital Implementation

By Shivareddy
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updated over 14 years ago by Kari

1 replies • 13199 views
Discussion

WIDE METAL ROUTES

Category: Digital Implementation

By tiEngr
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updated over 14 years ago by Kari

1 replies • 13142 views
Discussion

Digital Physical Design

Category: Digital Implementation

By Shaumik
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updated over 14 years ago by Kari

1 replies • 13011 views
Discussion

Need Help Troubleshooting SOC Encounter Violations

Category: Digital Implementation

By INSANI
•
updated over 14 years ago by Kari

1 replies • 13521 views
Discussion

clock tree file creation for multiple PLL scenario

Category: Digital Implementation

By gops
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updated over 14 years ago by Kari

1 replies • 13016 views
Discussion

Wires and standard cell buffers not in the bus guide after CTS and optDesign

Category: Digital Implementation

By enoorsal
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updated over 14 years ago by Kari

1 replies • 12954 views

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